AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 50

• Manufacturer Part Number: AD9510BCPZ
• Description: IC CLOCK DIST 8OUT PLL 64LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9510BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 8
• No. Of Multipliers / Dividers: 8
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9510
Reg.
Addr.
(Hex) Bit(s) Name
08
08
08
09
09
09
09
09
09
0A
<5:2> PLL Mux Control
<6>
<7>
<0>
<1>
<2>
<3>
<6:4> Charge Pump (CP)
<7>
<1:0> PLL Power-Down
Phase-Frequency
Detector (PFD)
Polarity
Reset All Counters 0 = Normal (Default), 1 = Reset R, A, and B Counters
N-Counter Reset
R-Counter Reset
Current Setting
Description
<5>
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MUXOUT is the PLL portion of the STATUS output MUX
0 = Negative (Default), 1 = Positive
Not Used
0 = Normal (Default), 1 = Reset A and B Counters
0 = Normal (Default), 1 = Reset R Counter
Not Used
<6>
0
0
0
0
1
1
1
1
Default = 000b
These currents assume: CPR
Actual current can be calculated by: CP_lsb = 3.06/CPR
Not Used
01 = Asynchronous Power-Down (Default)
<1>
0
0
1
1
<4>
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
<0>
0
1
0
1
<5>
0
0
1
1
0
0
1
1
<3>
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
<4>
0
1
0
1
0
1
0
1
Mode
Normal Operation
Asynchronous Power-Down
Normal Operation
Synchronous Power-Down
<2>
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. A | Page 50 of 60
SET
= 5.1 kΩ
I
0.60
1.2
1.8
2.4
3.0
3.6
4.2
4.8
CP
Off (Signal Goes Low) (Default)
Digital Lock Detect (Active High)
N Divider Output
Digital Lock Detect (Active Low)
R Divider Output
Analog Lock Detect (N Channel, Open-Drain)
A Counter Output
Prescaler Output (NCLK)
PFD Up Pulse
PFD Down Pulse
Loss-of-Reference (Active High)
Tri-State
Analog Lock Detect (P Channel, Open-Drain)
Loss-of-Reference or Loss-of-Lock (Inverse of DLD) (Active High)
Loss-of-Reference or Loss-of-Lock (Inverse of DLD) (Active Low)
Loss-of-Reference (Active Low)
MUXOUT—Signal on STATUS Pin
(mA)
SET