ICS8535AG-31LFT IDT, Integrated Device Technology Inc, ICS8535AG-31LFT Datasheet - Page 6
![IC FANOUT BUFFER 1-4 20-TSSOP](/photos/31/27/312709/20pin_tssop_sml.jpg)
ICS8535AG-31LFT
Manufacturer Part Number
ICS8535AG-31LFT
Description
IC FANOUT BUFFER 1-4 20-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Fanout Buffer (Distribution), Multiplexerr
Series
HiPerClockS™r
Datasheet
1.ICS8535AG-31LFT.pdf
(15 pages)
Specifications of ICS8535AG-31LFT
Number Of Circuits
1
Ratio - Input:output
2:4
Differential - Input:output
No/Yes
Input
LVCMOS, LVTTL, Crystal
Output
LVPECL
Frequency - Max
266MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
266MHz
Number Of Clock Inputs
2
Mode Of Operation
Single-Ended
Output Frequency
266MHz
Output Logic Level
LVPECL
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TSSOP
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Signal Type
LVCMOS/LVTTL
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
8535AG-31LFT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS8535AG-31LFT
Manufacturer:
IDT
Quantity:
20 000
IDT™ / ICS™ LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
ICS8535-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
8535AG-31
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
-100
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-190
-10
-20
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0
1k
Integrated
Circuit
Systems, Inc.
10k
www.icst.com/products/hiperclocks.html
O
A
FFSET
DDITIVE
100k
F
ROM
P
LVCMOS-
C
HASE
6
6
ARRIER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
L
OW
J
F
ITTER
1M
REQUENCY
S
TO
KEW
@ 155.52MHz (12kHz to 20MHz)
-3.3V LVPECL F
Additive Phase Jitter, RMS
, 1-
(H
Z
)
TO
-4, C
10M
= 0.057ps typical
RYSTAL
ANOUT
O
REV. B APRIL 29, 2005
SCILLATOR
100M
B
UFFER
ICS8535-31
TSD
/