ICS8535AG-31LF IDT, Integrated Device Technology Inc, ICS8535AG-31LF Datasheet - Page 8

• Manufacturer Part Number: ICS8535AG-31LF
• Description: IC FANOUT BUFFER 1-4 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8535AG-31LF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: No/Yes
• Input: LVCMOS, LVTTL, Crystal
• Output: LVPECL
• Frequency - Max: 266MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 266MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 266MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8535AG-31LF

IDT™ / ICS™ LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
ICS8535-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
C
The ICS8535-31 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 3 below were determined using an 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error.
8535AG-31
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
RTT =
ERMINATION FOR
RYSTAL
((V
F
FOUT
IGURE
OH
I
NPUT
+ V
OL
2A. LVPECL O
Integrated
Circuit
Systems, Inc.
) / (V
I
1
NTERFACE
LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50
= 50
18pF Parallel Crystal
Z
o
50
UTPUT
UTPUTS
A
T
RTT
X1
ERMINATION
Figure 3. C
50
PPLICATION
www.icst.com/products/hiperclocks.html
V
CC
FIN
- 2V
RYSTAL
C1
18p
C2
22p
LVCMOS-
8
8
I
These same capacitor values will tune any 18pF parallel reso-
nant crystal over the frequency range and other parameters
specified in this data sheet. The optimum C1 and C2 values
can be slightly adjusted for different board layouts.
50 transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
NFORMATION
XTAL_IN
XTAL_OUT
I
NPU
L
t I
OW
FOUT
NTERFACE
F
S
IGURE
TO
KEW
-3.3V LVPECL F
2B. LVPECL O
, 1-
Z
Z
o
o
= 50
= 50
TO
-4, C
125
84
RYSTAL
UTPUT
3.3V
125
84
T
ANOUT
ERMINATION
O
REV. B APRIL 29, 2005
FIN
SCILLATOR
B
UFFER
ICS8535-31
TSD
/