CY2292FXC Cypress Semiconductor Corp, CY2292FXC Datasheet - Page 2

• Manufacturer Part Number: CY2292FXC
• Description: IC 3PLL EPROM CLOCK GEN 16SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY2292FXC

• Package / Case: 16-SOIC (3.9mm Width)
• Pll: Yes
• Input: Clock, Crystal
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: No/No
• Frequency - Max: 66.6MHz, 90MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 66.6MHz/90MHz
• Mounting Style: SMD/SMT
• Max Output Freq: 200 MHz
• Number Of Outputs: 3
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: 0 C to + 70 C
• Supply Current: 70 mA
• Number Of Elements: 3
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 30MHz
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOIC
• Output Frequency Range: 0.076923 to 90MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-2042 - SOCKET ADAPTER FOR CY2071AFCY3095 - SOCKET ADAPTER FOR CY2292F428-1457 - KIT DEV FTG PROGRAMMING KIT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1745-5; CY2292FXC

Document #: 38-07449 Rev. *B
Pin Summary
Operation
The CY2292 is a third-generation family of clock generators.
The CY2292 is upwardly compatible with the industry standard
ICD2023 and ICD2028 and continues their tradition by
providing a high level of customizable features to meet the
diverse clock generation needs of modern motherboards and
other synchronous systems.
All parts provide a highly configurable set of clocks for PC
motherboard applications. Each of the four configurable clock
outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in
any combination. Multiple outputs configured for the same or
related
providing on-chip buffering for heavily loaded signals.
The CY2292 can be configured for either 5V or 3.3V operation.
The internal ROM tables use EPROM technology, allowing full
customization of output frequencies. The reference oscillator
has been designed for 10-MHz to 25-MHz crystals, providing
additional flexibility. No external components are required with
Notes:
CLKC
V
GND
XTALIN
XTALOUT
XBUF
CLKD
CPUCLK
CLKB
CLKA
S0
S1
S2/SUSPEND
SHUTDOWN/OE
1. For best accuracy, use a parallel-resonant crystal, C
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information.
4. The CY2292 has weak pull-downs on all outputs. Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.
DD
Pin Configurations
[3]
Name
[1]
frequencies will have low (
[1, 2]
Pin Number
CY2292
2, 14
3, 11
10
12
13
15
16
1
4
5
6
7
8
9
≤
Configurable clock output C.
Voltage supply.
Ground.
Reference crystal input or external reference clock input.
Reference crystal feedback.
Buffered reference clock output.
Configurable clock output D.
CPU frequency clock output.
Configurable clock output B.
Configurable clock output A.
CPU clock select input, bit 0.
CPU clock select input, bit 1.
CPU clock select input, bit 2. Optionally enables suspend feature when LOW.
Places outputs in three-state
places outputs in three-state
500 ps) skew, in effect
LOAD
XTALOUT
CPUCLK
≈ 17 pF or 18 pF.
XTALIN
XBUF
CLKD
CLKC
GND
V DD
16-pin SOIC
1
2
3
4
5
6
7
8
CY2292
16
15
14
13
12
11
10
9
[4]
[4]
this crystal. Alternatively, an external reference clock of
frequency between 1 MHz and 30 MHz can be used.
Output Configuration
The CY2292 has four independent frequency sources on-chip.
These are the reference oscillator, and three Phase-Locked
Loops (PLLs). Each PLL has a specific function. The System
PLL (SPLL) provides fixed output frequencies on the config-
urable outputs. The SPLL offers the most output frequency
divider options. The CPU PLL (CPLL) is controlled by the
select inputs (S0–S2) to provide eight user-selectable
frequencies with smooth slewing between frequencies. The
Utility PLL (UPLL) provides the most accurate clock. It is often
used for miscellaneous frequencies not provided by the other
frequency sources.
All configurations are EPROM programmable, providing short
sample and production lead times. Please refer to the appli-
cation note Understanding the CY2291, CY2292, and CY2295
for information on configuring the part.
condition and shuts down chip when LOW. Optionally, only
condition and does not shut down chip when LOW.
V DD
SHUTDOWN/OE
S2/SUSPEND
S1
S0
GND
CLKA
CLKB
Description
CY2292
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