CY23FP12OXC Cypress Semiconductor Corp, CY23FP12OXC Datasheet
CY23FP12OXC
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CY23FP12OXC
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CY23FP12OXC Summary of contents
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... N Test Logic Function Selection S[2:1] VSSC Cypress Semiconductor Corporation Document #: 38-07246 Rev. *E Functional Description The CY23FP12 is a high-performance fully field-program- mable 200 MHz zero delay buffer designed for high speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high-performance ASICs and microprocessors ...
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Pin Description Pin Name I/O 1 REF2 I 2 REF1 I 3 CLKB0 O 4 CLKB1 PWR SSB 6 CLKB2 O 7 CLKB3 PWR DDB 9 V PWR SSB 10 CLKB4 O 11 ...
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REF /M FBK /N Below is a list of independent functions that can be programmed with a volume or prototype programmer on the “default” silicon. Table 1. Configuration DC Drive Bank A Programs the drive strength of Bank A outputs. ...
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Table 1. (continued) Configuration Inv CLKB4 Generates an inverted clock on the CLKB4 output. When this option is programmed, CLKB4 and CLKB5 will become complimentary pairs. Pull-down Enable Enables/Disables internal pulldowns on all outputs Fbk Pull-down Enable Enables/Disables internal pulldowns ...
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Table list of output dividers that are independently selected to connect to each output pair. In the default (non-programmable) state of the device, S1 and S2 pins will function, as indicated in Table 4. Table 3. CLKA/B ...
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Absolute Maximum Conditions Parameter Description V Supply Voltage DD V Input Voltage REF IN V Input Voltage Except REF IN LU Latch-up Immunity I T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Operating Ambient A T Junction ...
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Switching Characteristics Parameter Description [6] Reference Frequency Reference Edge Rate Reference Duty Cycle [7] t Output Frequency 1 [5] Duty Cycle [5] t Rise Time 3 [5] t Fall Time 4 [8,9] TTB Total Timing Budget, Bank A and ...
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Switching Characteristics [5] Parameter Description t Tracking Skew tsk [5] t PLL Lock Time LOCK T Inserted Loop Delay LD Switching Waveforms Duty Cycle Timing 1.4V 1.4V All Outputs Rise/Fall Time 2.0V 2.0V OUTPUT 0.8V t ...
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... CY3672 Development Kit CY3692 CY23FP12S Socket (Label CY3672 ADP006) Lead-free CY23FP12OXC 28-pin SSOP CY23FP12OXCT 28-pin SSOP – Tape and Reel CY23FP12OXI 28-pin SSOP CY23FP12OXIT 28-pin SSOP – Tape and Reel Package Drawing and Dimension 28-lead (5.3 mm) Shrunk Small Outline Package O28 Total Timing Budget, TTB, Spread Aware, and CyberClocks are trademarks of Cypress Semiconductor Corporation ...
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Document History Page Document Title: CY23FP12 200-MHz Field Programmable Zero Delay Buffer Document Number: 38-07246 Orig. of REV. ECN NO. Issue Date Change ** 115158 07/03/02 *A 121880 12/14/02 *B 124523 03/19/03 *C 126938 06/16/03 *D 129364 09/10/03 *E 299718 ...