LMX2531LQ1570E/NOPB National Semiconductor, LMX2531LQ1570E/NOPB Datasheet - Page 18

• Manufacturer Part Number: LMX2531LQ1570E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2531LQ1570E/NOPB

• Pll: Yes
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 1.636GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.8 V ~ 3.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 1.6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2531LQ1570ETR

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1.0 Functional Description
The LMX2531 is a low power, high performance frequency
synthesizer system which includes the PLL, VCO, and par-
tially integrated loop filter. The following sections give a dis-
cussion of the various blocks of this device.
1.1 REFERENCE OSCILLATOR INPUT
Because the VCO frequency calibration algorithm is based on
clocks from the OSCin pin, there are certain bits that need to
be
XTLSEL (R6[22:20]) and XTLDIV (R7[9:8]) are both need to
be set based on the OSCin frequency, f
tions
XTLMAN (R7[21:10]) and XTLMAN2 (R8[4]) words need to
be set to the correct value.
1.2 R DIVIDER
The R divider divides the OSCin frequency down to the phase
detector frequency. The R divider value, R, is restricted to the
values of 1, 2, 4, 8, 16, and 32. If R is greater than 8, then this
also puts restrictions on the fractional denominator, FDEN,
than can be used. This is discussed in greater depth in later
sections.
1.3 PHASE DETECTOR AND CHARGE PUMP
The phase detector compares the outputs of the R and N di-
viders and puts out a correction current corresponding to the
phase error. The phase detector frequency, f
culated as follows:
Choosing R = 1 yields the highest possible phase detector
frequency and is optimum for phase noise, although there are
restrictions on the maximum phase detector frequency which
could force the R value to be larger. The far out PLL noise
improves 3 dB for every doubling of the phase detector fre-
quency, but at lower offsets, this effect is much less due to
the PLL 1/f noise. Aside from getting the best PLL phase
noise, higher phase detector frequencies also make it easier
to filter the noise that the delta-sigma modulator produces,
which peaks at an offset frequency of f
The LMX2531 also has 16 levels of charge pump currents and
a highly flexible fractional modulus. Increasing the charge
pump current improves the phase noise about 3 dB per dou-
bling of the charge pump current, although there are small
diminishing returns as the charge pump current increases.
From a loop filter design and PLL phase noise perspective,
one might think to always design with the highest possible
phase detector frequency and charge pump current. Howev-
er, if one considers the worst case fractional spurs that occur
at an output frequency equal to 1 channel spacing away from
a multiple of the f
If the phase detector frequency or charge pump currents are
too high, then these spurs could be degraded, and the loop
filter may not be able to filter these spurs as well as theoreti-
cally predicted. For optimal spur performance, a phase de-
tector frequency around 2.5 MHz and a charge pump current
of 1X are recommended.
1.4 N DIVIDER AND FRACTIONAL CIRCUITRY
The N divider in the LMX2531 includes fractional compensa-
tion and can achieve any fractional denominator between 1
and 4,194,303. The integer portion, N
of the N divider value and the fractional portion, N
the remaining fraction. So in general, the total N divider value,
N, is determined by:
set
and
depending
for
OSCin
, then this gives reason to reconsider.
low
f
PD
= f
on
OSCin
OSCin
the
/ R
Integer
PD
OSCin
OSCin
frequencies,
/2 from the carrier.
, is the whole part
. For some op-
PD
, can be cal-
frequency.
Fractional
the
, is
18
For example, if the phase detector frequency (f
MHz and the VCO frequency (f
would be 173.61. This would imply that N
N
tions that are arise due to the architecture of this divider. The
first restrictions arise because the N divider value is actually
formed by a quadruple modulus 16/17/20/21 prescaler, which
creates minimum divide values. N
because the LMX2531 due to the fractional engine of the N
divider.
The fractional word, N
NUM and DEN words. In the example used here with the
fraction of 61/100, NUM = 61 and DEN = 100. The fractional
denominator value, DEN, can be set from 2 to 4,194,303. The
case of DEN=0 makes no sense, since this would cause an
infinite N value; the case of 1 makes no sense either (but
could be done), because integer mode should be used in
these applications. All other values in this range, like 10, 32,
42, 734, or 4,000,000 are all valid. Once the fractional de-
nominator, DEN, is determined, the fractional numerator,
NUM, is intended to be varied from 0 to DEN-1.
In general, the fractional denominator, DEN, can be calculat-
ed by dividing the phase detector frequency by the greatest
common divisor (GCD) of the channel spacing (f
phase detector frequency. If the channel spacing is not obvi-
ous, then it can be calculated as the greatest common divisor
of all the desired VCO frequencies.
For example, consider the case of a 10 MHz phase detector
frequency and a 200 kHz channel spacing at the VCO output.
The greatest common divisor of 10 MHz and 200 kHz is just
200 kHz. If one takes 10 MHz divided by 200 kHz, the result
is 50. So a fractional denominator of 50, or any multiple of 50
would work in this example. Now consider a case with a 10
MHz phase detector frequency and a 30 kHz channel spac-
ing. The greatest common divisor of 10 MHz and 30 kHz is
10 kHz. The fractional denominator therefore must be a mul-
tiple 1000, since this is 10 MHz divided by 10 kHz. For a final
example, consider an application with a fixed output frequen-
cy of 2110.8 MHz and a OSCin frequency of 19.68 MHz. If the
phase detector frequency is chosen to be 19.68 MHz, then
the channel spacing can be calculated as the greatest com-
mon multiple of 19.68 MHz and 2110.8 MHz, which is 240
kHz. The fractional denominator is therefore a multiple of 41,
which is 19.68 MHz / 240 kHz. Refer to application note 1865
for more details on frequency planning.
To achieve a fractional N value, an integer N divider is mod-
ulated between different values. This gives rise to three main
degrees of freedom with the LMX2531 delta sigma engine in-
cluding the modulator order, dithering, and the way that the
fractional portion is expressed. The first degree of freedom is
the modulator order, which gives the user the ability to opti-
mize for a particular application. The modulator order can be
selected as zero (integer mode), two, three, or four. One sim-
ple technique to better understand the impact of the delta
sigma fractional engine on noise and spurs is to tune the VCO
to an integer channel and observe the impact of changing the
modulator order from integer mode to a higher order. The
higher the fractional modulator order is, the lower the spurs
theoretically are. However, this is not always the case, and
the higher order fractional modulator can sometimes give rise
to additional spurious tones, but this is dependent on the ap-
plication. The second degree of freedom with the LMX2531
Fractional
is 61/100. N
FDEN = k · f
N = N
Integer
Fractional
k = 1, 2, 3 ..
Integer
has some minimum value restric-
PD
/ GCD(f
, is a fraction formed with the
+ N
VCO
Fractional
) was 1736.1 MHz, then N
Integer
PD
, f
is further restricted
CH
Integer
)
PD
CH
is 173 and
) was 10
) and the