CY25812ZXC Cypress Semiconductor Corp, CY25812ZXC Datasheet - Page 8

• Manufacturer Part Number: CY25812ZXC
• Description: IC CLOCK GEN 3.3V SS 8-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock/Frequency Synthesizer, Frequency Modulator, Spread Spectrum Clock Generatorr

Specifications of CY25812ZXC

• Number Of Circuits: 1
• Package / Case: 8-TSSOP
• Pll: Yes
• Input: Clock, Crystal, Resonator
• Output: Clock
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 64MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 64MHz
• Maximum Input Frequency: 32 MHz
• Minimum Input Frequency: 4 MHz
• Output Frequency Range: 8 MHz to 64 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AC Electrical Specifications
(Industrial Grade) (continued)
Characteristic Curves
The following curves demonstrate the characteristic behavior of CY25811/12/14 when tested over a number of environmental and
application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in DC
and AC Specification tables.
Document Number: 38-07112 Rev. *I
T
T
T
T
T
Parameter
DCOUT
CCJ1
CCJ2
CCJ3
SU
600
500
400
300
200
100
30
28
26
24
22
20
18
16
14
12
10
0
4
4
Jitter vs. Input Frequency (No Load)
4.5
Output Clock Duty Cycle
Cycle to Cycle Jitter, Spread on
Cycle to Cycle Jitter, Spread on
Cycle to Cycle Jitter, Spread on
PLL Lock Time
IDD vs. Frequency (FRSEL = 0, 1, M)
8
Frequency (MHz), no load, normalized to FRSEL = 0, (4 - 8 MHz).
5
12
5.5
Description
Input Frequency (MHz)
FRSEL = M
16 - 32 MHz
16
FRSEL = 1
8 - 16 MHz
6
20
6.5
FRSEL = 0
4 - 8 MHz
24
7
Figure 3. Characteristic Curves
7.5
SSCLK
Fin = 6 MHz, CY25811/12/14
Fin = 12 MHZ, CY25811/12/14
Fin = 24 MHz, CY25811/12/14
From V
28
8
DD
32
= 3.0V to valid SSCLK
Condition
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
1.9
1.8
3
2
2.75
2.25
1.75
2.8
2.5
2
-40
2.9
-25
-10
3
Bandwidth % vs. VDD
Bandwidth % vs. Temperature
8.0 MHz
5
3.1
VDD (volts)
20
3.2
35
Temp (C)
Min
40
3.3
–
–
–
–
50
3.4
65
CY25811/12/14
4.0 MHz
Max
650
630
520
60
4
80
3.5
95
3.6
Page 8 of 14
6.0 MHz
32.0 MHz
110
Unit
ms
ps
ps
ps
%
3.7
125
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