CY23EP09SXC-1 Cypress Semiconductor Corp, CY23EP09SXC-1 Datasheet - Page 2

• Manufacturer Part Number: CY23EP09SXC-1
• Description: IC CLK ZDB 9OUT 220MHZ 16SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY23EP09SXC-1

• Number Of Circuits: 1
• Package / Case: 16-SOIC (3.9mm Width)
• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Ratio - Input:output: 1:9
• Differential - Input:output: No/No
• Frequency - Max: 133MHz, 167MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 220MHz
• Maximum Input Frequency: 167 MHz
• Minimum Input Frequency: 10 MHz
• Output Frequency Range: 10 MHz to 167 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-07760 Rev. *B
Pin Definition
Select Input Decoding
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
The output driving the CLKOUT pin will be driving a total load
of 5 pF plus any additional load externally connected to this
pin. For applications requiring zero input-output delay, the total
load on each output pin (including CLKOUT) must be the
same. If input-output delay adjustments are required, the
CLKOUT load may be changed to vary the delay between the
REF input and remaining outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information refer to the application note
entitled “CY2305 and CY2309 as PCI and SDRAM Buffers”.
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
S2
0
0
1
1
Pin
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
S1
0
1
0
1
CLKB3
CLKB4
GND
V
CLKA3
CLKA4
CLKOUT
REF
CLKA1
CLKA2
V
GND
CLKB1
CLKB2
S2
S1
DD
DD
[3]
[3]
[1]
CLOCK A1–A4
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
Three-state
[2]
Signal
Driven
Driven
Driven
CLOCK B1–B4
Input reference frequency
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V or 2.5V supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3V or 2.5V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
Three-state
Three-state
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
[4]
Description
Output Source
Reference
PLL
PLL
PLL
PLL Shutdown
CY23EP09
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N
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