NBC12439AFNG ON Semiconductor, NBC12439AFNG Datasheet - Page 4

• Manufacturer Part Number: NBC12439AFNG
• Description: IC CLOCK SYNTH 50-800MHZ 28-PLCC
• Manufacturer: ON Semiconductor
• Type: PLL Clock Generatorr

Specifications of NBC12439AFNG

• Pll: Yes
• Input: Crystal
• Output: PECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/Yes
• Frequency - Max: 800MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 800MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á
explicitly stated, all inputs are CMOS/TTL compatible with either pull−up or pulldown resistors. The PECL outputs are
capable of driving two series terminated 50 W transmission lines on the incident edge.
* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.
INPUTS
OUTPUTS
POWER
Table 3. PIN FUNCTION DESCRIPTION
XTAL1, XTAL2
S_LOAD*
S_DATA*
S_CLOCK*
P_LOAD**
M[6:0]**
N[1:0]**
OE**
FREF_EXT*
XTAL_SEL**
PWR_DOWN
FOUT, FOUT
TEST
V
PLL_V
GND
−
The following gives a brief description of the functionality of the NBC12439 and NBC12349A Inputs and Outputs. Unless
CC
Pin Name
CC
Crystal Inputs
CMOS/TTL Serial Latch Input
(Internal Pulldown Resistor)
CMOS/TTL Serial Data Input
(Internal Pulldown Resistor)
CMOS/TTL Serial Clock Input
(Internal Pulldown Resistor)
CMOS/TTL Parallel Latch Input
(Internal Pullup Resistor)
CMOS/TTL PLL Loop Divider
Inputs (Internal Pullup Resistor)
CMOS/TTL Output Divider Inputs
(Internal Pullup Resistor)
CMOS/TTL Output Enable Input
(Internal Pullup Resistor)
CMOS/TTL Input
(Internal Pulldown Resistor)
CMOS/TTL Input
(Internal Pullup Resistor)
CMOS/TTL Input
(Internal Pulldown Resistor)
PECL Differential Outputs
CMOS/TTL Output
Positive Supply for the Logic
Positive Supply for the PLL
Negative Power Supply
Exposed Pad for QFN−32 only
Function
These pins form an oscillator when connected to an external series−resonant
crystal.
This pin loads the configuration latches with the contents of the shift registers.
The latches will be transparent when this signal is HIGH; thus, the data must be
stable on the HIGH−to−LOW transition of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
This pin loads the configuration latches with the contents of the parallel inputs
.The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW−to−HIGH transition of P_LOAD for proper opera-
tion.
These pins are used to configure the PLL loop divider. They are sampled on the
LOW−to−HIGH transition of P_LOAD. M[6] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled
on the LOW−to−HIGH transition of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the FOUT output. When Disabled, FOUT goes LOW and
FOUT.
This pin can be used as the PLL Reference
This pin selects between the crystal and the FREF_EXT source for the PLL refer-
ence signal. A HIGH selects the crystal input.
PWR_DOWN forces the FOUT outputs to synchronously reduce frequency by a
factor of 16.
These differential, positive−referenced ECL signals (PECL) are the outputs of the
synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
The positive supply for the internal logic and output buffer of the chip, and is con-
nected to +3.3 V or +5.0 V.
This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
These pins are the negative supply for the chip and are normally all connected to
ground.
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be at-
tached to a heat−sinking conduit. The pad is electrically connected to GND.
http://onsemi.com
4
Description