NBC12439AFNG ON Semiconductor, NBC12439AFNG Datasheet - Page 9

• Manufacturer Part Number: NBC12439AFNG
• Description: IC CLOCK SYNTH 50-800MHZ 28-PLCC
• Manufacturer: ON Semiconductor
• Type: PLL Clock Generatorr

Specifications of NBC12439AFNG

• Pll: Yes
• Input: Crystal
• Output: PECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/Yes
• Frequency - Max: 800MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 800MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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accomplished by properly configuring the internal dividers
to produce the desired frequency at the outputs. The output
frequency can by represented by this formula:
This can be simplified to:
where F
modulus, and N is the output divider modulus. Note that it
is possible to select values of M such that the PLL is unable
to achieve loop lock. To avoid this, always make sure that M
is selected to be 25 ≤ M ≤ 50 for a 16 MHz input reference.
See Table 11.
above equation reduces to:
Substituting the four values for N (1, 2, 4, 8) yields:
*For crystal frequency of 16 MHz.
desired frequency from the above equations. The four output
frequency ranges established by N are 400−800 MHz,
200 − 400 MHz,
respectively. From these ranges, the user will establish the
value of N required. The value of M can then be calculated
based on Equation 1. For example, if an output frequency of
384 MHz was desired, the following steps would be taken to
identify the appropriate M and N values. 384 MHz falls
within the frequency range set by an N value of 2; thus, N
[1:0]
For N = 2, F
M = 384 B 8 = 48, so M[6:0] = 0110000. Following this same
procedure, a user can generate a selected frequency. The size
of the programmable frequency steps of F
to F
Table 11, which shows the usable VCO frequency and M
divider range.
Table 10. Programmable Output Divider Function
Table
F
F
N1
Programming the NBC12439 and NBC12439A is
Assuming that a 16 MHz reference frequency is used the
1
0
0
1
The user can identify the proper M and N values for the
For input reference frequencies other than 16 MHz, see
OUT
OUT
XTAL
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+ (F
+ (F
N0
XTAL
1
0
1
0
÷ N.
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XTAL
XTAL
N Divider
OUT
is the crystal frequency, M is the loop divider
B1
B2
B4
B8
or FREF_EXT B 2)
or FREF_EXT)
= 8M and M = F
100 − 200 MHz and
F OUT + 16M B N
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M
M
M
M
F
OUT
=
16
8
4
2
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M B N
Range (MHz)*
Output Fre-
OUT
400−800
200−400
100−200
quency
50−100
2 M B N
OUT
B 8. Therefore,
50 − 100 MHz,
PROGRAMMING INTERFACE
will be equal
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16 MHz
8 MHz
4 MHz
2 MHz
F
http://onsemi.com
(eq. 1)
(eq. 2)
Step
(eq. 3)
OUT
00.
9
divider M is limited by the VCO frequency range and
fXTAL. M must be configured to match the VCO frequency
range of 400 to 800 MHz in order to achieve stable PLL
operation.
stability. If the value for M fell outside of the valid range, a
different N value would be selected to move M in the
appropriate direction.
parallel or serial interface. The parallel interface is
controlled via the P_LOAD signal such that a LOW to HIGH
transition will latch the information present on the M[6:0]
and N[1:0] inputs into the M and N counters. When the
P_LOAD signal is LOW, the input latches will be
transparent and any changes on the M[6:0] and N[1:0] inputs
will affect the FOUT output pair. To use the serial port, the
S_CLOCK signal samples the information on the S_DATA
line and loads it into a 12 bit shift register. Note that the
P_LOAD signal must be HIGH for the serial load operation
to function. The Test register is loaded with the first three
bits, the N register with the next two, and the M register with
the final nine bits of the data stream on the S_DATA input.
For each register, the most significant bit is loaded first (T2,
N1, and M6). The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters. A
pulse on the S_LOAD pin after the shift register is fully
loaded will transfer the divide values into the counters.
Figures 5 and 6 illustrate the timing diagram for both a
parallel and a serial load of the device synthesizer.
through the parallel interface, and then possibly, fine tuned
again through the serial interface. This approach allows the
application to ramp up at one frequency and then change or
fine−tune the clock as the ability to control the serial
interface becomes available.
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. The T2, T1, and T0 control bits are preset
to ‘000’ when P_LOAD is LOW so that the PECL FOUT
outputs are as jitter−free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter
of the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select one
of the alternate functions for this pin.
The input frequency and the selection of the feedback
The value for M falls within the constraints set for PLL
The M and N counters can be loaded either through a
M[6:0] and N[1:0] are normally specified after power−up
The TEST output provides visibility for one of the several
M min + f VCOmin B F XTAL and
M max + f VCOmax B F XTAL
(eq. 4)
(eq. 5)