AD809BR Analog Devices Inc, AD809BR Datasheet - Page 3

• Manufacturer Part Number: AD809BR
• Description: IC SYNTH FREQ 155.52MHZ 16-SOIC
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizerr

Specifications of AD809BR

• Rohs Status: RoHS non-compliant
• Pll: No
• Input: CMOS, ECL, PECL, TTL
• Output: ECL, PECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 155.52MHz
• Divider/multiplier: No/No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 155MHz

Pin
No. Mnemonic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD809 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PECLINN
PECLIN
V
CLKOUTN
CLKOUT
V
CF1
CF2
AV
TTL/CMOSIN TTL/CMOS Reference Clock Input
AV
CLKINN
CLKIN
AV
MUX
V
CC2
CC1
EE
EE
CC1
CC2
CLKOUTN
PECLINN
CLKOUT
PECLIN
PIN CONFIGURATION
V
V
CF1
CF2
CC2
CC1
PIN DESCRIPTIONS
Differential 155 MHz Input
Differential 155 MHz Input
Differential 155 MHz Output
Description
Digital V
Differential 155 MHz Output
Digital V
Loop Damping Capacitor
Loop Damping Capacitor
Analog V
Analog V
PECL Differential Reference Clock Input
PECL Differential Reference Clock Input
Analog V
Input Signal Mux Control Input
Digital V
1
2
3
4
5
6
7
8
(Not to Scale)
TOP VIEW
AD809
CC
CC
EE
CC
EE
CC
for PECL Outputs
for Internal Logic
for PLL
for Input Stage
16
15
14
13
12
11
10
9
V
MUX
AV
CLKIN
CLKINN
AV
TTL/CMOSIN
AV
EE
CC2
CC1
EE
–3–
Input Reference
PECL/ECL Differential
TTL/CMOS
Single-Ended
AD809 Phase Skew
The AD809 output is in phase with the input. The falling edge
at Pin 4, CLKOUTN, occurs 700 ps before the rising edge at
Pin 10, TTL/CMOSIN at 27 C. The phase skew remains rela-
tively constant over temperature. Refer to Table III for phase
skew data.
Temperature
( C)
–35
–20
0
10
30
50
70
80
90
100
Table II. Applying a PECL/ECL or CMOS/TTL Reference
Input to the AD809
Table III. Phase Skew vs. Temperature
MUX Input
TTL “0”
TTL “1”
Skew (CLKOUTN, Pin 4, Relative to
TTL/CMOSIN, Pin 10 Measured in
ps at Package Pins)
–1000
–950
–850
–750
–700
–600
–450
–450
–350
–250
AD809 Configuration
Apply the valid PECL–level reference
frequency to Pins 13 and 12.
AD809 frequency synthesizer ignores
the input at Pin 10.
Apply the reference frequency to
Pin 10.
Connect Pins 13 and 12 to AV
(Pins 9 and 16). The AD809 senses
the common-mode signal at these pins
as less than valid PECL and selects the
TTL/CMOS input as active.
Table I.
Input Selected
CLKIN/CLKINN
PECLIN/PECLINN
WARNING!
ESD SENSITIVE DEVICE
AD809
EE