AD809BR Analog Devices Inc, AD809BR Datasheet - Page 5

• Manufacturer Part Number: AD809BR
• Description: IC SYNTH FREQ 155.52MHZ 16-SOIC
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizerr

Specifications of AD809BR

• Rohs Status: RoHS non-compliant
• Pll: No
• Input: CMOS, ECL, PECL, TTL
• Output: ECL, PECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 155.52MHz
• Divider/multiplier: No/No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 155MHz

REV. A
USING THE AD809
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended.
Power Supply Connections
Use of a 10 F capacitor between V
mended. Care should be taken to isolate the +5 V power trace
to V
vide the CLKOUT/CLKOUTN signals.
Use of a trace connecting Pin 14 and Pin 6 (AV
respectively) is recommended. Use of 0.1 F capacitors between
IC power supply and ground is recommended. Power supply
decoupling should take place as close to the IC as possible.
Refer to the schematic, Figure 5, for advised connections.
Transmission Lines
Use of 50
inputs.
Terminations
Termination resistors should be used for PECL input signals.
Metal, thick film, 1% tolerance resistors are recommended.
Termination resistors for the PECL input signals should be
placed as close as possible to the PECL input pins.
Connections from the power supply to load resistors for input
and output signals should be individual, not daisy chained. This
will avoid crosstalk on these signals.
Loop Damping Capacitor, C
A ceramic capacitor may be used for the loop damping capaci-
tor. A 22 nF capacitor provides a damping factor of 10.
CC2
CLKOUTN
CLKOUT
ECL INN
(Pin 3). The V
ECL IN
VECTOR PINS SPACED FOR THROUGH-HOLE
CAPACITOR ON VECTOR CUPS.
COMPONENT SHOWN FOR REFERENCE ONLY.
transmission lines are recommended for PECL
J2 C3 0.1µF
J1 C2 0.1µF
J3
J4
0.1µF
C6
C5 0.1µF
C4 0.1µF
100
R3
CC2
R4
100
pin is used inside the device to pro-
D
3.65k
JUMPER
0.1µF
R7 100
R8 100
R6
C1
154
R11
CC
W2
and ground is recom-
R5
301
49.9
R12
154
R1
TP3
Figure 5. Evaluation Board Schematic
+5V
CC2
TP1
10µF
C11
TP2
R2
49.9
GND
and V
CD
TP4
C8
C7
1
2
3
4
5
6
7
CC1
8
SOLDERED TO BOARD
GUARD RING
PECLINN
V
CLKOUTN
CLKOUT
CF1
CF2
PECLIN
V
CC2
CC1
EQUAL LENGTH
50 STRIP LINE
16-PIN SOIC
AD809
–5–
TTL/CMOSIN
Synthesizer Input
TTL/CMOSIN
Synthesizer Input
CLKIN/CLKINN
PECL INPUT
PLL Differential
Output Stage–
CLKOUT/CLKOUTN
CLKINN
AV
CLKIN
AV
AV
MUX
V
CC2
CC1
EE
EE
16
15
14
13
12
11
10
9
NOTE:
JUMPER
GND
W1
C9
C10
ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TPx
Figure 4. Simplified Schematics
EXT
C7–C10 ARE 0.1µF BYPASS CAPACITORS
RIGHT ANGLE SMA CONNECTOR
OUTER SHELL TO GND PLANE
TEST POINTS ARE VECTOR PINS
+5V
R16
301
JUMPER
W3
J5
49.9
R14
MUX
460
500
500
R13
49.9
500
R15
49.9
7.5k
2.6mA
460
3.65k
40µA
0.1µF
C12
R17
C15 0.1µF
C13 0.1µF
C14 0.1µF
2*I
80µA
V
0µA
V
OR
CC1
TTL
EE
7.5k
V
EE
J6
J7
J8
V
V
CC1
EE
AD809
CLKIN
CMOS/TTL IN
CLKINN
2*I
80µA
0µA
DIFFERENTIAL
OUTPUT
OR
V
TTL
CC2
I
TTL
40µA