CY2308SXC-5HT Cypress Semiconductor Corp, CY2308SXC-5HT Datasheet - Page 3

• Manufacturer Part Number: CY2308SXC-5HT
• Description: IC CLK ZDB 8OUT 133MHZ 16SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY2308SXC-5HT

• Number Of Circuits: 1
• Package / Case: 16-SOIC (3.9mm Width)
• Pll: Yes
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 66.67MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 133MHz
• Output Frequency Range: 10 MHz to 133.3 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Available CY2308 Configurations
Zero Delay and Skew Control
To close the feedback loop of the CY2308, the FBK pin is driven
from any of the eight available output pins. The output driving the
FBK pin drives a total load of 7 pF plus any additional load that
it drives. The relative loading of this output to the remaining
outputs adjusts the input-output delay. This is shown in the
Figure
For applications requiring zero input-output delay, all outputs
including the one providing feedback is equally loaded.
Document Number: 38-07146 Rev. *H
Note
CY2308–1
CY2308–1H
CY2308–2
CY2308–2
CY2308–3
CY2308–3
CY2308–4
CY2308–5H
5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.
Figure 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading between FBK Pin and CLKA/CLKB Pins
2.
Device
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Feedback From
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference /2
Bank A Frequency
If input-output delay adjustments are required, use the
Delay and Skew Control
between the feedback output and remaining outputs.
For zero output-output skew, outputs are loaded equally. For
further information on using CY2308, refer to the application note
“CY2308: Zero Delay Buffer.”
Reference
Reference
Reference/2
Reference
Reference or Reference
2 X Reference
2 X Reference
Reference /2
graph to calculate loading differences
Bank B Frequency
[5]
CY2308
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Zero
[+] Feedback