CY28339ZXC Cypress Semiconductor Corp, CY28339ZXC Datasheet - Page 8

• Manufacturer Part Number: CY28339ZXC
• Description: IC CLOCK SYNTHESIZER 48-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Spread Spectrum Clock Generatorr

Specifications of CY28339ZXC

• Pll: Yes
• Input: LVTTL, Crystal
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 8:16
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP II
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07507 Rev. *A
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 3.0 ms.
CPU_STOP# Clarification
The CPU_STOP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function.
CPU_STP#
REF 14.318MHz
66Buff1 / GMCH
CPU# 133M Hz
CPU 133MHz
USB 48MHz
PCIF / APIC
PW RDW N#
PCI 33M Hz
CPUC
CPUC
CPUT
CPUT
33MHz
66Buff
3V66
66In
Figure 4. Power-down Deassertion Timing Waveforms – Buffered Mode
Figure 5. CPU_STOP# Assertion Waveform
<1.8m S
CPU_STOP# Assertion
When CPU_STOP# pin is asserted, all CPUT/C outputs that
are set with the SMBus configuration to be stoppable via
assertion of CPU_STOP# will be stopped after being sampled
by two falling CPUT/C clock edges. The final state of the
stopped CPU signals is CPUT = HIGH and CPU0C = LOW.
There is no change to the output drive current values during
the stopped state. The CPUT is driven HIGH with a current
value equal to (Mult 0 “select”) × (Iref), and the CPUC signal
will not be driven. Due to external pull-down circuitry CPUC will
be LOW during this stopped state.
400uS m ax
30uS m in
CY28339
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