CY25200-ZXC002AT Cypress Semiconductor Corp, CY25200-ZXC002AT Datasheet
CY25200-ZXC002AT
Specifications of CY25200-ZXC002AT
Related parts for CY25200-ZXC002AT
CY25200-ZXC002AT Summary of contents
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... Programmable Spread Spectrum Clock Generator for EMI Reduction Description The CY25200 is a programmable clock generator with spread spectrum capability. Spread spectrum modulates the output clock frequency over a small range, spreading the energy and reducing the energy peak. This is a powerful technique to reduce EMI in a variety of applications ...
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... The range for down spread is from –0.5% to –5.0%. Contact the factory for smaller or larger spread % amounts, if required. The input to the CY25200 is either a crystal or a clock signal. The input frequency range for crystals MHz and for clock signals 166 MHz. ...
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... Function USER SPECIFIED Programming Description Field-Programmable CY25200 The CY25200 is programmed at the package level, and must be programmed prior to installation on a circuit board. Field programmable devices are denoted by an “F” in the ordering code, and are blank when shipped. The CY25200 is Flash technology based, which allows reprogrammed up to 100 times ...
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... In this example, the configurable pins SSCLK5 (pin 14) and SSCLK6 (pin 15) are used as output clocks. Input Frequency (XIN, Pin 1 and XOUT, Pin 16) The input to the CY25200 is a crystal or a clock. The input fre- quency range for crystals MHz, and for clock signal 166 MHz. C ...
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... MHz 15 VDD 2 REFOUT(14.318 MHz) 14 REFOUT(14.318MHz) AVDD 3 13 VSS CLKSEL 4 12 AVSS 5 33.33/66.66 MHz 11 VSSL VDDL 6 10 33.33/66.66 MHz SSON 7 9 33.33/66.66 MHz 33.33/66.66 MHz 8 CY25200 SSCLK4 REFOUT REFOUT (Pin 12) (Pin 14) (Pin 15) 33.33 14.318 14.318 66.66 14.318 14.318 Page [+] Feedback ...
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... SSCLK (Asynchronous ) V DD OUTPUT ENABLE 0V SSCLK (Asynchronous ) Document #: 38-07633 Rev. *F Figure 4. Duty Cycle Timing ( )/SR1 (or SR3) DD )/SR2 (or SR4) DD Figure 6. Power Down and Power Up Timing High Impedance t STP Figure 7. Output Enable and Disable Timing OE2 V IL High Impedance T OE1 a CY25200 / Page [+] Feedback ...
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... Fnominal 65.5 65 64 160 180 200 67.5 67 66.5 66 Fnominal 65 160 180 200 CY25200 Fmod=30kHz, Spread%= -4% Fnominal 100 120 140 160 180 200 Time (us) Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% Fnominal 100 120 140 160 180 200 Time (us) ...
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... DDL CMOS levels, 70 CMOS levels, 30 Current Current (V = 2.625V) DDL DDL V Current (V = 3.465V) DDL DDL 3.465V DD DDL 3.465V DD DDL DD CY25200 Min Typ. Max Unit 8 30 MHz Ω 25 values Min Typ Max Unit 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 2.625 ...
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... Time from rising edge outputs at a valid frequency (Asynchronous) SSCLK1/2/3/4/5/6 Time from rising edge on PD# to outputs at valid frequency (Asynchronous) Time from rising edge on PD# to outputs at valid frequency (Asynchronous) Output to output skew between related clock outputs. Measured at V /2. DD CY25200 Min Typ Max Unit ...
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... TSSOP – Tape and Reel (Pb-free) CY25200KFZXC 16-Pin TSSOP (Pb-free) CY25200KFZXCT 16-Pin TSSOP – Tape and Reel (Pb-free) CY3672-USB Programmer for Field Programmable Devices CY3695 CY22050/CY22150/CY25200 Socket Adapter for CY3672-USB Table 5. 16-Pin TSSOP Package Characteristics Parameter θ JA Package Drawing and Dimensions 1 4 ...
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... Document History Page Document Title: CY25200 Programmable Spread Spectrum Clock Generator for EMI Reduction Document Number: 38-07633 Orig. of Submission REV. ECN NO. Change ** 204243 RGL *A 220043 RGL *B 267832 RGL *C 291094 RGL *D 1821908 DPF/AESA *E 2442066 KVM/AESA *F 2758387 KVM/AESA 09/01/2009 Document #: 38-07633 Rev. *F Description of Change ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07633 Rev. *F All products and company names mentioned in this document may be the trademarks of their respective holders. psoc.cypress.com clocks.cypress.com image.cypress.com Revised September 01, 2009 CY25200 Page [+] Feedback ...