SI4133GX2-BM Silicon Laboratories Inc, SI4133GX2-BM Datasheet - Page 15

• Manufacturer Part Number: SI4133GX2-BM
• Description: SYNTH DUAL GSM RF(RF1/RF2/IF)
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4133GX2-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
The Si4133G-X2 is a monolithic integrated circuit that
performs IF and dual-band RF synthesis for many
wireless applications such as GSM 850, E-GSM 900,
DCS 1800, and PCS 1900. Its fast transient response
also makes the Si4133G-X2 especially well suited to
GPRS and HSCSD multislot applications where
channel switching and settling times are critical. This
integrated circuit (IC), with a minimum number of
external components, is all that is necessary to
implement the frequency synthesis function.
The Si4133G-X2 has three complete phase-locked
loops
oscillators (VCOs). The low phase noise of the VCOs
makes the Si4133G-X2 suitable for use in demanding
cellular applications. Phase detectors, loop filters, and
reference dividers are also integrated. The IC is
programmed through a three-wire serial interface.
One PLL is provided for IF synthesis, and two PLLs are
provided for dual-band RF synthesis. One RF VCO is
optimized to have its center frequency set between
947 and 1720 MHz, whereas the second RF VCO is
optimized to have its center frequency set between
789 and 1429 MHz. Each RF PLL can adjust its output
frequency by ±5% relative to its VCO’s center
frequency. The IF VCO is optimized to have its center
frequency set to 1080 MHz. Three settings are provided
for IF output frequencies of 1070.4, 1080 and
1089.6 MHz.
The center frequency of each of the three VCOs is set
by
Inaccuracies in the value of the inductance are
compensated for by the Si4133G-X2’s proprietary self-
tuning algorithm. This algorithm is initiated each time
the PLL is powered-up (by either the PWDN pin or by
software) and/or each time a new output frequency is
programmed.
The two RF PLLs share a common output pin, so only
one PLL is active at a time. Because the two VCOs can
be set to have widely separated center frequencies, the
RF output can be programmed to service different
frequency bands, therefore the Si4133G-X2 ideal for
use in dual-band cellular handsets.
The unique PLL architecture used in the Si4133G-X2
produces a transient response that is superior in speed
to fractional-N architectures without suffering the high
phase noise or spurious modulation effects often
associated with those designs.
the
(PLLs)
connection
with
of
integrated
an
external
voltage-controlled
inductance.
Rev. 1.2
Serial Interface
The Si4133G-X2 is programmed serially with 22-bit
words comprised of 18-bit data fields and 4-bit address
fields. Figure 3 on page 7 shows the format of the serial
interface. A timing diagram for the serial word is shown
in Figure 2 on page 7.
When the serial interface is enabled (i.e., when SEN is
low) data and address bits on the SDATA pin are
clocked into an internal shift register on the rising edge
of SCLK. Data in the shift register is then transferred on
the rising edge of SEN into the internal data register
addressed in the address field. The serial word is
disabled when SEN is high.
Table 9 on page 19 summarizes the Data register
functions and addresses. It is not necessary (although it
is permissible) to clock into the internal shift register any
leading bits that are “don’t cares”.
Setting the VCO Center Frequencies
The PLLs can adjust the IF and RF output frequencies
±5% with respect to their VCO center frequencies. Each
center frequency is established by the value of an
external inductance connected to the respective VCO.
Manufacturing tolerances of ±10% for the external
inductances
compensates for inaccuracies in each inductance by
executing a self-tuning algorithm following powerup or
following
frequency.
Because the total tank inductance is in the low nH
range, the inductance of the package must be
considered
inductance. The total inductance (L
each VCO is the sum of the external inductance (L
and the package inductance (L
nominal capacitance (C
inductance, and the center frequency is as follows:
a
F
CEN
in
change
are
F
=
CEN
determining
-------------------------------------------------------------------------
2π
acceptable.
(
=
L
PKG
------------------------------------------- -
2π
or
in
NOM
L
+
TOT
the
) in parallel with the total
Si4133G-X2
CL
1
1
PKG
×
the
EXT
C
programmed
NOM
). Each VCO has a
) C
The
TOT
×
correct
NOM
) presented to
Si4133G-X2
external
output
EXT
15
)