SI4133GX2-BM Silicon Laboratories Inc, SI4133GX2-BM Datasheet - Page 16

• Manufacturer Part Number: SI4133GX2-BM
• Description: SYNTH DUAL GSM RF(RF1/RF2/IF)
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4133GX2-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Si4133G-X2
Tables 6 and 7 summarize these characteristics for
each VCO.
As a design example, consider a design that is required
to synthesize frequencies in a 25 MHz band between
1120 and 1145 MHz. The center frequency should be
defined as midway between the two extremes, or
1132.5 MHz. The PLL can adjust the VCO output
frequency ±5% of the center frequency, or ±56.6 MHz of
1132.5 MHz
1189 MHz, more than enough for this example). The
RF2 VCO has a C
inductance in parallel with this capacitance yields the
16
Figure 15. External Inductance Connection
Table 7. Si4133G-XM2 VCO Characteristics
VCO f
Table 6. Si4133G-XT2 VCO Characteristics
VCO f
RF1
RF2
RF1
RF2
IF
IF
Min
CEN
Min
CEN
947
789
947
789
(MHz)
(MHz)
1080
1080
Range
Range
(i.e.,
1720
1429
1720
1429
Max
Max
Si4133G-XM2
from
NOM
L
L
C
C
PKG
PKG
2
2
(pF)
(pF)
4.3
4.8
6.5
4.3
4.8
6.5
NOM
NOM
of 4.8 pF, and a 4.1 nH
approximately
L
L
(nH)
(nH)
2.0
2.3
2.1
PKG
1.5
1.5
1.6
PKG
L
L
Min
Min
0.0
0.3
0.5
1.1
EXT
EXT
(nH)
(nH)
1.2
1.7
Range
Range
1076
L
EXT
Max
Max
5.1
7.0
4.6
6.2
Rev. 1.2
to
required center frequency. An external inductance of
1.8 nH should be connected between RFLC and RFLD
as shown in Figure 15. This, in addition to 2.3 nH of
package
inductance to the VCO. In manufacturing, the external
inductance can vary ±10% of its nominal value and the
Si4133G-X2 corrects for the variation with the self-
tuning algorithm.
In most cases the requisite value of the external
inductance is small enough to utilize a PC board trace.
During
approximating the required inductance can be used. For
more information, refer to AN31: Inductor Design for the
Si41xx Synthesizer Family.
Self-Tuning Algorithm
The self-tuning algorithm is initiated immediately
following powerup of a PLL or, if the PLL is already
powered, following a change in its programmed output
frequency. This algorithm attempts to tune the VCO so
that its free-running frequency is near the required
output frequency. The algorithm compensates for
manufacturing tolerance errors in the value of the
external inductance connected to the VCO. It also
reduces the frequency error for which the PLL must
correct to get precisely the required output frequency.
The self-tuning algorithm leaves the VCO oscillating at
a frequency in error by less than 1% of the required
output frequency.
After self-tuning, the PLL controls the VCO oscillation
frequency. The PLL completes frequency locking,
eliminating remaining frequency error. From then on, it
maintains frequency-lock, compensating for effects
caused by temperature and supply voltage variations.
The Si4133G-X2’s self-tuning algorithm compensates
for component value errors at any temperature within
the specified temperature range. However, the ability of
the PLL to compensate for drift in component values
that occur after self-tuning is limited. For external
inductances
approximately ±150 ppm/
for changes in temperature of approximately ±30
Applications where the PLL is regularly powered down
or switched between channels minimize or eliminate the
potential effects of temperature drift because the VCO is
re-tuned when it is powered up or when a new
frequency is programmed. In applications where the
ambient temperature can drift substantially after self-
tuning, it may be necessary to monitor the LDETB (lock-
detect bar) signal on the AUXOUT pin to determine the
locking state of the PLL. (See the AUXILIARY OUTPUT
section below for how to select LDETB.)
initial
inductance,
board
with
layout,
presents
o
C, the PLL can maintain lock
temperature
a
the
length
correct
coefficients
of
o
C.
trace
total