SI5310-GM Silicon Laboratories Inc, SI5310-GM Datasheet - Page 12

• Manufacturer Part Number: SI5310-GM
• Description: IC CLOCK MULT/REGENERATER 20MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5310-GM

• Number Of Circuits: 1
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Pll: Yes with Bypass
• Input: Clock
• Output: CML
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 668MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 668MHz
• Maximum Input Frequency: 668 MHz
• Minimum Input Frequency: 9.375 MHz
• Output Frequency Range: 150 MHz to 668 MHz
• Supply Voltage (max): 2.625 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1292-5

Si5310
4. Functional Description
The Si5310 is an integrated clock multiplier and clock
regenerator device based on SIlicon Laboratories
DSPLL™ technology. The DSPLL phase locks to the
clock input signal (CLKIN) and generates a phase-
locked output clock (MULTOUT) at a multiple of the
input clock frequency. The DSPLL is also employed to
regenerate an output clock (CLKOUT) that is a jitter-
attenuated version of the input clock with clean rising
and falling edges.
12
Note:
(MULTOUT = 600–668 MHz)
(MULTOUT = 150–167 MHz)
1. The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be
2. The CLKOUT output is not valid for MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.)
asynchronous to the CLKIN input, but must be within ±100 ppm of the stated CLKIN multiple.
MULTSEL
0
1
Table 9. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges
150.000–167.000
300.000–334.000
600.000–668.000
150.000–167.000
37.500–41.750
75.000–83.500
18.750–20.875
37.500–41.750
75.000–83.500
CLKIN Range
9.375–10.438
(MHz)
Rev. 1.2
REFCLK = 2
n = –5, –4, –3, –2, –1
n = –6, –5, –4, –3, –2
n = –4, –3, –2, –1, 0
n = –4, –3, –2, –1, 0
n = –3, –2, –1, 0, 1
n = –3, –2, –1, 0, 1
n = –2, –1, 0, 1, 2
n = –2, –1, 0, 1, 2
n = –1, 0, 1, 2, 3
The MULTOUT output is configured to operate in either
the 150–167 MHz or the 600–668 MHz frequency range
using the MULTSEL control input. A reference clock
input signal (REFCLK) is used by the DSPLL as a
reference for determination of the PLL lock status. For
convenience, REFCLK can be provided at any one of
five frequencies, each a multiple of the CLKIN
frequency. The REFCLK rate is automatically detected,
so no control inputs are needed for configuration. The
REFCLK input can be synchronous or asynchronous
with respect to the CLKIN input. The operating ranges
for the CLKIN, CLKOUT, MULTOUT, and REFCLK
signals are indicated in Table 9. Typical values for
several applications are presented in Table 10.
n = 0, 1, 2, 3, 4
(See Note 1)
±100 ppm
n
x CLKIN
See Note 2
See Note 2
CLKOUT
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
MULTOUT
16xCLKIN
16xCLKIN
2xCLKIN
8xCLKIN
4xCLKIN
1xCLKIN
8xCLKIN
4xCLKIN
2xCLKIN
1xCLKIN