Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 136
![IC 6MHZ Z80 CMOS CTC 28-PDIP](/photos/6/57/65755/269-28-dip_sml.jpg)
Z84C3006PEG
Manufacturer Part Number
Z84C3006PEG
Description
IC 6MHZ Z80 CMOS CTC 28-PDIP
Manufacturer
Zilog
Type
Counter/Timer Circuit (CTC)r
Series
Z80r
Specifications of Z84C3006PEG
Frequency
6MHz
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 100°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
Z84C3xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
6 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Filter Terminals
SMD
Ic Generic Number
84C30
Operating Temperature Min
-40°C
Operating Temperature Max
100°C
Clock Frequency
6MHz
Rohs Compliant
Yes
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
28
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
Details
Other names
269-3910
Z84C3006PEG
Z84C3006PEG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z84C3006PEG
Manufacturer:
ZILOG
Quantity:
1 980
Company:
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Z84C3006PEG
Manufacturer:
Zilog
Quantity:
1 722
Company:
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Z84C3006PEG
Manufacturer:
ZILOG
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1 980
Company:
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Z84C3006PEG
Manufacturer:
WSI
Quantity:
4 970
Part Number:
Z84C3006PEG
Manufacturer:
ZILOG
Quantity:
20 000
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116
Operation:
Op Code:
Operands:
Description: The contents of the register pair qq are pushed to the external memory
Condition Bits Affected: None
Example:
UM008005-0205
Z80 CPU
User’s Manual
(SP-2) ← qqL, (SP-1) ← qqH
PUSH
qq
LIFO (last-in, first-out) Stack. The Stack Pointer (SP) register pair holds the
16-bit address of the current top of the Stack. This instruction first
decrements SP and loads the high order byte of register pair qq to the
memory address specified by the SP. The SP is decremented again and
loads the low order byte of qq to the memory location corresponding to this
new address in the SP. The operand qq identifies register pair BC, DE, HL,
or AF, assembled as follows in the object code:
If the AF register pair contains
1007H, at instruction
memory address
1005H
1
1
.
M Cycles
Pair
q
BC
DE
HL
AF
3
q
1005H
PUSH AF
0
PUSH qq
contains
1
11 (5, 3, 3)
T States
2233H
memory address
0
qq
00
01
10
11
33H
1
, and the Stack Pointer contains
and the Stack Pointer contains
4 MHz E.T.
1006H
2.75
Z80 Instruction Set
contains
22H
,
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