CY2XF33FLXIT Cypress Semiconductor Corp, CY2XF33FLXIT Datasheet - Page 5

• Manufacturer Part Number: CY2XF33FLXIT
• Description: IC XTAL OSC CMOS 6CLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY2XF33FLXIT

• Pll: Yes
• Input: Crystal
• Output: LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/Yes
• Frequency - Max: 690MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 6-CLCC
• Frequency: *
• Count: *
• Operating Supply Voltage (typ): 2.5/3.3
• Output Level: LVDS
• Symmetry Max: 60%
• Operating Temp Range: -40C to 85C
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Absolute Maximum Conditions
Operating Conditions
DC Electrical Characteristics
Document Number: 001-53148 Rev. *D
V
V
T
T
ESD

V
T
T
I
V
V
V
V
V
V
I
I
I
I
C
C
Parameter
Parameter
Parameter
Notes
DD
IH0
IH1
IL0
IL1
1. The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
3. I
4. Not 100% tested, guaranteed by design and characterization.
A
DD
IN
S
J
DD
PU
OD
OS
IH
IL
JA
IN0
IN1
OD
OS
[1]
[3]
[2]
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
[4]
[4]
DD
HBM
includes ~4 mA of current that is dissipated externally in the output termination resistors.
Supply voltage
Input voltage, DC
Temperature, storage
Temperature, junction
ESD protection (human body model)
Thermal resistance, junction to ambient 0 m/s airflow
3.3 V supply voltage range
2.5 V supply voltage range
Power up time for V
monotonic)
Ambient temperature (commercial)
Ambient temperature (industrial)
Operating supply current
LVDS differential output voltage
Change in V
complementary output states
LVDS offset output voltage
Change in V
complementary output states
Input high voltage
Input Low voltage
Input high current, FS0 pin
Input high current, FS1 pin
Input low current, FS0 pin
Input low current, FS1 pin
Input capacitance, FS0 pin
Input capacitance, FS1 pin
OD
OS
Description
Description
between
between
DD
to reach minimum specified voltage (power ramp is
Description
V
terminated
V
terminated
V
as terminated in
V
as terminated in
V
as terminated in
V
between CLK and CLK#
–
Input = V
Input = V
Input = V
Input = V
–
–
–
–
Relative to V
Non operating
–
JEDEC STD 22-A114-B
DD
DD
DD
DD
DD
DD
= 3.465 V, CLK = 150 MHz, output
= 2.625 V, CLK = 150 MHz, output
= 3.3 V or 2.5 V, defined in
= 3.3 V or 2.5 V, defined in
= 3.3 V or 2.5 V, defined in
= 3.3 V or 2.5 V, R
DD
DD
SS
SS
SS
Condition
Condition
Figure 2
Figure 2
Figure 2
TERM
= 100
Figure 3
Figure 3
Figure 4
0.7*V
3.135
2.375
1.125
2000
0.05
–0.5
–0.5
Min
Min
–40
Min
247
–50
–20
–55
–40
0
–
–
–
–
–
–
–
–
–
DD
64
V
DD
Max
135
135
Typ
Typ
4.4
3.3
2.5
15
–
–
–
–
–
–
4
–
–
–
–
–
–
–
–
–
–
+0.5
0.3*V
3.465
2.625
1.375
Max
Max
500
120
454
115
115
70
85
50
50
10
–
–
–
–
–
CY2XF33
DD
C/W
Page 5 of 11
Unit
C
C
V
V
V
Unit
Unit
ms
mA
mA
mV
mV
mV
A
A
A
A
C
C
pF
pF
V
V
V
V
V
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