M48T08Y-10MH1F STMicroelectronics, M48T08Y-10MH1F Datasheet - Page 9

• Manufacturer Part Number: M48T08Y-10MH1F
• Description: IC TIMEKPR SRAM 64KBIT 5V 28SOIC
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T08Y-10MH1F

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC, 28-SOH (8.48mm Width)
• Bus Type: Parallel
• User Ram: 8KB
• Operating Supply Voltage (typ): 5V
• Package Type: SOH
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 28
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4710-2

M48T08, M48T08Y, M48T18
2.1
Figure 5.
Note:
A0-A12
E1
E2
G
DQ0-DQ7
READ mode
The M48T08/18/08Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip
enable 1) is low, and E2 (chip enable 2) is high. The device architecture allows ripple-
through access of data from eight of 65,536 locations in the static storage array. Thus, the
unique address specified by the 13 address inputs defines which one of the 8,192 bytes of
data is to be accessed. Valid data will be available at the data I/O pins within address access
time (t
access times are also satisfied. If the E1, E2 and G access times are not met, valid data will
be available after the latter of the chip enable access times (t
enable access time (t
The state of the eight three-state data I/O signals is controlled by E1, E2 and G. If the
outputs are activated before t
until t
will remain valid for output data hold time (t
address access.
READ mode AC waveforms
WRITE enable (W) = high.
AVQV
AVQV
. If the address inputs are changed while E1, E2 and G remain active, output data
) after the last address input signal is stable, providing that the E1, E2, and G
GLQV
tE2HQX
tE1LQX
tAVQV
tE2HQV
tE1LQV
tGLQX
).
tGLQV
AVQV
Doc ID 2411 Rev 10
, the data lines will be driven to an indeterminate state
VALID
tAVAV
AXQX
) but will go indeterminate until the next
VALID
tGHQZ
E1LQV
or t
E2HQV
Operation modes
tAXQX
tE1HQZ
tE2LQZ
) or output
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