M48T35-70PC1 STMicroelectronics, M48T35-70PC1 Datasheet - Page 11

• Manufacturer Part Number: M48T35-70PC1
• Description: IC TIMEKPR NVRAM 256KBIT 5V 28DI
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T35-70PC1

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.75 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Function: Clock/Calendar/NV Timekeeping RAM/Watchdog Timer/Battery Backup
• Rtc Memory Size: 32768 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Parallel
• Bus Type: Parallel
• User Ram: 32KB
• Operating Supply Voltage (typ): 5V
• Package Type: PCDIP
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.75V
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 28
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2845-5

M48T35, M48T35Y
Table 4.
1. Valid for ambient operating temperature: T
2. C
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Note:
t
t
WHQX
WLQZ
Symbol
t
t
t
t
t
t
t
noted).
t
t
t
t
t
t
WLWH
WHAX
WHDX
DVWH
AVWH
AVWL
EHAX
EHDX
ELEH
DVEH
AVEH
AVAV
AVEL
L
= 5 pF.
(2)(3)
(2)(3)
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
WRITE mode AC characteristics
Data retention mode
With valid V
Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
become high impedance, and all inputs are treated as “Don't care” (see
page
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
user can be assured the memory will be in a write protected state, provided the V
is not less than t
into the deselect window during the time the device is sampling V
of the power supply lines is recommended.
When V
preserves data and powers the clock. The internal button cell will maintain data in the
M48T35/Y for an accumulated period of at least 7 years when V
system power returns and V
supply is switched to external V
plus t
WRITE cycles prior to processor stabilization. Normal RAM operation can resume t
V
For more information on battery storage life refer to the application note AN1012.
CC
exceeds V
rec
19,
CC
(min). E should be kept high as V
Table
drops below V
CC
Parameter
applied, the M48T35/Y operates as a conventional BYTEWIDE static RAM.
PFD
10, and
F
. The M48T35/Y may respond to transient noise spikes on V
(max).
CC
Table 11 on page
(1)
A
SO
= 0 to 70 or –40 to 85 °C; V
falls within the V
CC
, the control circuit switches power to the internal battery which
Doc ID 2611 Rev 9
rises above V
CC
. Write protection continues until V
20).
CC
PFD
SO
rises past V
(max), V
, the battery is disconnected, and the power
CC
Min
70
50
55
30
30
60
60
0
0
0
0
5
5
5
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
M48T35/Y
PFD
PFD
(min) window. All outputs
(min) to prevent inadvertent
CC
CC
Max
25
is less than V
. Therefore, decoupling
CC
reaches V
Figure 12 on
Operation modes
PFD
CC
(min), the
CC
that reach
SO
PFD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
rec
. As
fall time
(min)
after
11/28