ISL12024IBZ-T Intersil, ISL12024IBZ-T Datasheet - Page 22

• Manufacturer Part Number: ISL12024IBZ-T
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12024IBZ-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12024IBZ-TTR

Alarm Operation Examples
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm0 set with single interrupt (IM = “0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm0 registers as follows:
B. Also, the AL0E bit must be set as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1” and also bringing the IRQ/F
low.
EXAMPLE 2
Pulsed interrupt once per minute (IM = “1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm0 registers as follows:
B. Set the Interrupt register as follows:
REGISTER
REGISTER
CONTROL
ALARM0
2.7V TO 5.5V
MOA0
DWA0
MNA0
HRA0
SCA0
DTA0
INT
FIGURE 24. SUPER CAPACITOR CHARGING CIRCUIT
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0 HEX
0 0 1 0 0 0 0 0
V
DD
BIT
V
BIT
SS
22
V
BAT
B0h Minutes set to 30,
00h Seconds disabled
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
x0h Enable Alarm
enabled
enabled
enabled
enabled
disabled
SUPER CAP
DESCRIPTION
DESCRIPTION
OUT
output
ISL12024
Once the registers are set, the following waveform will be
seen at IRQ/F
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
I
Operation in Battery Backup Mode is affected by the BSW
and SBIB bits as described earlier. These bits allow flexible
operation of the serial bus and EEPROM in Battery Backup
Mode, but certain operational details need to be clear before
utilizing the different modes. Table 8 describes four different
modes possible with using the BSW and SBIB bits, and how
they affect the serial interface and battery backup operation.
• Mode A - In this mode, selection bits indicate a Standard
• Mode B - In this mode selection, bits indicate Legacy
• Mode C - This mode combines Standard Mode battery
REGISTER
REGISTER
CONTROL
2
ALARM0
C Communications During Battery Backup
Mode switchover combined with I
Backup Mode. When the V
lower of V
Backup Mode. If the microcontroller and bus pull-ups are
also powered by the battery, then the ISL12024 can
communicate in Battery Backup Mode.
Mode switchover combined with I
Backup Mode. When the V
the device will enter Battery Backup Mode. If the
microcontroller and bus pull-ups are also powered by the
battery, then the ISL12024 can communicate in Battery
Backup Mode. This mode places the ISL12024 device in
the same operating mode as the X1226 legacy device.
switchover with no I
When the V
DWA0
MNA0
MOA0
SCA0
HRA0
DTA0
INT
RTC AND ALARM REGISTERS ARE BOTH 30s
7 6 5 4 3 2 1 0 HEX
1 0 1 0 0 0 0 0 x0h Enable Alarm and Int
TRIP
7 6 5 4 3 2 1 0 HEX
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
0 0 0 0 0 0 0 0 00h Minutes disabled
0 0 0 0 0 0 0 0 00h Hours disabled
0 0 0 0 0 0 0 0 00h Date disabled
0 0 0 0 0 0 0 0 00h Month disabled
0 0 0 0 0 0 0 0 00h Day of week disabled
OUT
DD
or V
voltage drops below the lower of V
:
BAT
2
C operation in Battery Backup Mode.
BIT
BIT
, then the device will enter Battery
60s
DD
DD
voltage drops below the
voltage drops below V
2
2
C operation in Battery
C operation in Battery
Mode
enabled
DESCRIPTION
DESCRIPTION
August 18, 2008
TRIP
FN6370.3
BAT
or
,