ISL12026IBZ Intersil, ISL12026IBZ Datasheet - Page 11

• Manufacturer Part Number: ISL12026IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12026IBZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Format: HH
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Memory Configuration: 512 X 8
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output (IRQ/
F
AL0E or both bits are set to ‘1’ and both the FO1 and FO0
bits are set to 0 (F
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
“1”. The IRQ/F
alarm occurs. This means that once the interrupt mode
alarm is set, it will continue to alarm for each occurring
match of the alarm and present time. This mode is
convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or
utility meter reading.
In the case that both Alarm 0 and Alarm 1 are enabled, the
IRQ/F
the RTC (both alarms can provide hardware interrupt). If the
IM bit is also set to "1", the IRQ/F
of the alarms as well.
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the IRQ/
F
output. When using this function, the Alarm output function is
disabled.
OUT
OUT
FO1
0
0
0
0
1
1
1
1
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
0
0
1
1
). The interrupts are enabled when either the AL1E or
OUT
output pin. Table 4 shows the selection bits for this
0
0
1
1
0
0
1
1
FO0
pin will be pulsed each time either alarm matches
0
1
0
1
0
1
0
1
0
1
0
1
OUT
PROTECTED ADDRESSES
OUT
output will now be pulsed each time an
disabled).
None (Default)
180
100
000
000
000
000
000
Alarm output (F
TABLE 3.
ISL12026
OUTPUT FREQUENCY
h
h
h
h
h
h
h
11
– 1FF
– 1FF
– 1FF
– 03F
– 07F
– 0FF
– 1FF
OUT
32.768kHz
4096Hz
h
h
h
h
h
h
h
1Hz
will be pulsed for each
OUT
disabled)
ARRAY LOCK
First 16 Pages
First 4 Pages
First 8 Pages
Upper 1/4
Upper 1/2
Full Array
Full Array
None
ISL12026
Oscillator Compensation Registers
There are two trimming options.
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64 to +110 ppm of total
adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation.
The effective on-chip series load capacitance, C
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C
controlled capacitors, C
and X2 pins to ground (see Figure 8). The value of C
C
The effective series load capacitance is the combination of
C
For example, C
100000) = 4.5pF, and C
The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
C
C LOAD
C
X2
X1
LOAD
X
- ATR. Analog Trimming Register
- DTR. Digital Trimming Register
=
is given by the following formula:
and C
(
16 b5
=
=
⋅
---------------------------------- -
⎛
⎝
⎛
⎝
16 b5
---------------------------------------------------------------------------------------------------------------------------- -
X2
---------- -
C
1
X1
+
:
⋅
8 b4
X1
X2
1
+
LOAD
⋅
FIGURE 8. DIAGRAM OF ATR
---------- -
C
+
1
8 b4
X2
LOAD
+
⋅
4 b3
⎞
⎠
(ATR = 00000) = 12.5pF, C
C
C
X1
X2
⋅
+
X1
LOAD
4 b3
is changed via two digitally
+
⋅
and C
2 b2
⋅
(ATR = 011111) = 20.25pF.
+
2 b2
2
+
⋅
X2
1 b1
⋅
OSCILLATOR
, connected from the X1
+
CRYSTAL
1 b1
+
⋅
0.5 b0
+
⋅
0.5 b0
+
⋅
LOAD
9
LOAD
October 23, 2006
)pF
+
9
X1
⎞ pF
⎠
(ATR =
,
FN8231.5
and