DS1371U+ Maxim Integrated Products, DS1371U+ Datasheet - Page 12

• Manufacturer Part Number: DS1371U+
• Description: IC BINARY COUNTER 32-BIT 8-USOP
• Manufacturer: Maxim Integrated Products
• Type: Binary Counterr

Specifications of DS1371U+

• Time Format: Binary
• Date Format: Binary
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Counter Type: Binary Counters
• Number Of Bits: 32
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Clock Frequency: 400kHz
• Supply Voltage Range: 1.7V To 5.5V
• No. Of Pins: 8
• Clock Format: Binary
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS1371
Data valid: The state of the data line represents valid data when, after a START condition, the
data line is stable for the duration of the high period of the clock signal. The data on the line must
be changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition.
The number of data bytes transferred between the START and the STOP conditions is not limited,
and is determined by the master device. The information is transferred byte-wise and each
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receiver acknowledges with a ninth bit. Within the I
C bus specifications a standard mode
(100kHz clock rate) and a fast mode (400kHz clock rate) are defined.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device must generate an extra clock pulse, which is
associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related
clock pulse. Setup and hold times must be taken into account. A master must signal an end of data
to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the
slave. In this case, the slave must leave the data line HIGH to enable the master to generate the
STOP condition.
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Figure 4. I
C Data Transfer Overview
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