DS1371U+ Maxim Integrated Products, DS1371U+ Datasheet - Page 9

• Manufacturer Part Number: DS1371U+
• Description: IC BINARY COUNTER 32-BIT 8-USOP
• Manufacturer: Maxim Integrated Products
• Type: Binary Counterr

Specifications of DS1371U+

• Time Format: Binary
• Date Format: Binary
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Counter Type: Binary Counters
• Number Of Bits: 32
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Clock Frequency: 400kHz
• Supply Voltage Range: 1.7V To 5.5V
• No. Of Pins: 8
• Clock Format: Binary
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS1371
Time-of-Day Counter
The time-of-day counter is a 32-bit up counter. The contents can be read or written by accessing the
address range 00h–03h. When the counter is read, the current time of day is latched into a register, which
is output on the serial data line while the counter continues to increment. Writing to the counter resets the
countdown chain for the time-of-day counter (Figure 2). The watchdog countdown chain is unaffected. If
the square-wave output is enabled and is set to 1Hz, the output resets when the countdown chain is reset.
Because the other square-wave frequencies are derived before the section of the countdown chain that is
reset, the other frequencies are unaffected by a write to the time-of-day counter.
Watchdog/Alarm Counter
If the counter is not needed, it can be disabled and used as a 24-bit cache of NV RAM by setting the
WACE bit in the control register to logic 0. If all 24 bits of the watchdog/alarm counter are written to
zero, the counter is disabled, independent of the WACE bit setting. When the watchdog counter is written
to a nonzero value, and WACE is written to logic 1, the function of the counter is determined by the
WD/ALM bit.
Note: The WDS input must be low when writing to the watchdog counter registers.
When the WD/ALM bit in the control register is set to a logic 0, the WD/ALM counter decrements every
second until it reaches zero. At this point, the AF bit in the status register is set to a 1 and the counter is
reloaded and restarted. AF remains set until cleared by writing it to a 0. If INTCN = AIE = 1, the
SQW/INT pin will go active whenever AF = 1.
Note: WACE must be set to a logic 1 after the alarm value is written.
When the WD/ALM bit is set to logic 1, the WD/ALM counter decrements every 1/4096 of a second
(approximately every 244μs) until it reaches zero. When any of the watchdog counters bytes are read, the
seed value is reloaded and the counter restarts. Writing to the watchdog counter updates the seed value
and reloads the counter with the new seed value. A low to high transition on the WDS input reloads and
restarts the counter with the seed value. When the counter reaches zero, the AF bit is set and the counter
stops. The AF bit remains set until cleared by writing it to 0. If INTCN and AIE are both at logic 1 when
the AF bit becomes set, the SQW/INT pin pulses low for 250ms. At the end of the 250ms pulse, the AF
bit is cleared and SQW/INT becomes high impedance.
Note: WACE must be toggled from a logic 0 to a logic 1 after the watchdog counter is written from a
zero to a nonzero value.
The 250ms pulse on SQW/INT cannot be truncated by writing either AF or AIE to zero during the low
time. If the WD/ALM counter is written during the 250ms pulse, the counter starts decrementing upon the
pulse completion.
9 of 15