M41T56M6E STMicroelectronics, M41T56M6E Datasheet - Page 7

• Manufacturer Part Number: M41T56M6E
• Description: IC SRAM SRL TIMEKPR 512BIT 8SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/NVSRAMr

Specifications of M41T56M6E

• Memory Size: 56B
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Function: Clock/Calendar
• Rtc Memory Size: 64 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (2-Wire, I2C)
• Nvram Features: RTC, Internal Battery, XTAL
• Interface Type: I2C, Serial, 2-Wire
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2818-5; M41T56M6

2
2.1
2.1.1
2.1.2
Operation
The M41T56 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 64 bytes
contained in the device can then be accessed sequentially in the following order:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The clock continually monitors V
V
Inputs to the device will not be recognized at this time to prevent erroneous data from being
written to the device from an out of tolerance system. When V
automatically switches over to the battery and powers down into an ultra low current mode
of operation to conserve battery life. Upon power-up, the device switches from battery to
V
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
●
●
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain High.
Start data transfer
A change in the state of the data line, from High to Low, while the clock is High, defines the
START condition.
PFD
CC
Seconds register
Minutes register
Century/hours register
Day register
Date register
Month register
Years register
Control register
RAM
at V
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is High.
Changes in the data line while the clock line is High will be interpreted as control
signals.
, the device terminates an access in progress and resets the device address counter.
BAT
and recognizes inputs when V
CC
for an out of tolerance condition. Should V
CC
goes above V
PFD
CC
falls below V
volts.
BAT
CC
, the device
fall below
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