M48T02-70PC1 STMicroelectronics, M48T02-70PC1 Datasheet - Page 9

• Manufacturer Part Number: M48T02-70PC1
• Description: IC TIMEKPR NVRAM 16KBIT 5V 24-DI
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T02-70PC1

• Memory Size: 16K (2K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.75 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (600 mil) Module
• Function: Clock/Calendar/NV Timekeeping RAM/Battery Backup
• Rtc Memory Size: 2048 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2827-5

M48T02, M48T12
2.2
Figure 5.
Figure 6.
A0-A10
E
W
DQ0-DQ7
A0-A10
E
W
DQ0-DQ7
WRITE mode
The M48T02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
to the initiation of another READ or WRITE cycle. Data-in must be valid t
end of WRITE and remain valid for t
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
WRITE enable controlled, WRITE AC waveform
Chip enable controlled, WRITE AC waveforms
tAVEL
tAVEL
tAVWL
tAVWL
tWLQZ
Doc ID 2410 Rev 8
tAVWH
tAVEH
EHAX
tWLWH
VALID
tAVAV
VALID
WHDX
tAVAV
tELEH
from chip enable or t
afterward. G should be kept high during WRITE
WLQZ
tDVEH
tDVWH
DATA INPUT
after W falls.
DATA INPUT
tWHDX
WHAX
tEHDX
tWHQX
from WRITE enable prior
tEHAX
tWHAX
DVWH
Operation modes
prior to the
AI01332B
AI01331
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