M48T37Y-70MH1E STMicroelectronics, M48T37Y-70MH1E Datasheet - Page 17

• Manufacturer Part Number: M48T37Y-70MH1E
• Description: IC TIMEKPR NVRAM 256KBIT5V 44SOH
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T37Y-70MH1E

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-SOH
• Bus Type: Parallel
• User Ram: 32KB
• Operating Supply Voltage (typ): 5V
• Package Type: SOH
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 44
• Mounting: Surface Mount
• Memory Configuration: 32K X 8
• Nvram Features: RTC
• Interface Type: Parallel
• Access Time: 70ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 44
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2854-5; M48T37Y-70MH1

Programmable Interrupts
The M48T37Y/V provides two programmable in-
terrupts: an alarm and a watchdog. When an inter-
rupt condition occurs, the M48T37Y/V sets the
appropriate flag bit in the Flag Register 7FF0h.
The interrupt enable bits (AFE and ABE) in 7FF6h
and the Watchdog Steering (WDS) Bit in 7FF7h al-
low the interrupt to activate the IRQ/FT pin.
The Alarm flag and the IRQ/FT output are cleared
by a READ to the Flags Register. An interrupt con-
dition reset will not occur unless the addresses are
stable at the flag location for at least 15ns while
the device is in the READ Mode as shown in
ure 8., page
The IRQ/FT pin is an open drain output and re-
quires a pull-up resistor (10k
V
unless an interrupt occurs or the Frequency Test
Mode is enabled.
Battery Low Flag
The M48T37Y/V automatically performs periodic
battery voltage monitoring upon power-up. The
Battery Low Flag (BL), Bit D4 of the Flags Register
7FF0h, will be asserted high if the SNAPHAT
battery is found to be less than approximately
2.5V. The BL Flag will remain active until comple-
tion of battery replacement and subsequent bat-
Table 7. Default Values
Note: 1. WDS, BMB0-BMB4, RBO, RB1.
Initial Power-up
(Battery Attach for SNAPHAT)
Subsequent Power-up / RESET
Power-down
CC
. The pin remains in the high impedance state
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
4. Assuming these bits set to '1' prior to power-down.
(4)
14.
Condition
(2)
(3)
recommended) to
W
0
0
0
Fig-
®
R
0
0
0
tery low monitoring tests during the next power-up
sequence.
If a battery low is generated during a power-up se-
quence, this indicates the battery voltage is below
2.5V (approximately), which may be insufficient to
maintain data integrity. Data should be considered
suspect and verified as correct. A fresh battery
should be installed. The SNAPHAT top may be re-
placed while VCC is applied to the device.
Note: This will cause the clock to lose time during
the interval the battery/crystal is removed.
Note: Battery monitoring is a useful technique only
when performed periodically. The M48T37Y/V
only monitors the battery when a nominal V
applied to the device. Thus applications which re-
quire extensive durations in the battery back-up
mode should be powered-up periodically (at least
once every few months) in order for this technique
to be beneficial. Additionally, if a battery low is in-
dicated, data integrity should be verified upon
power-up via a checksum or other technique.
Initial Power-on Defaults
Upon application of power to the device, the fol-
lowing register bits are set to a '0' state: WDS;
BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; and FT
(see Table 7).
FT
0
0
0
AFE
0
0
1
ABE
M48T37Y, M48T37V
0
0
1
WATCHDOG
Register
0
0
0
(1)
CC
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