ISL12024IRTCZ-T Intersil, ISL12024IRTCZ-T Datasheet - Page 9

• Manufacturer Part Number: ISL12024IRTCZ-T
• Description: IC RTC/CALENDER 64BIT 8-TDFN
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12024IRTCZ-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a 24-hour
format. If the MIL bit is 0, the RTC uses a 12-hour format,
and the H21 bit functions as an AM/PM indicator with a ‘1’
representing PM. The clock defaults to standard time with
H21 = 0.
Leap Years
Leap years add the day February 29 and are defined as
those years that are divisible by 4.
Status Register (SR)
The Status Register is located in the CCR memory map at
address 003Fh. This is a volatile register only, and is used to
control the WEL and RWEL write enable latches, read power
status and two alarm bits. This register is separate from both
the array and the Clock/Control Registers (CCR).
BAT: Battery Supply - Volatile
This bit set to “1” indicates that the device is operating from
V
hardware (ISL12024IRTCZ internally). Once the device
begins operating from V
AL1, AL0: Alarm Bits - Volatile
These bits announce if either alarm 0 or alarm 1 match the
real-time clock. If there is a match, the respective bit is set to
‘1’. The falling edge of the last data bit in a SR Read
operation resets the flags. (Note: Only the AL bits that are
set when an SR read starts will be reset). An alarm bit that is
set by an alarm occurring during an SR read operation will
remain set after the read operation is complete.
Default
ADDR
003Fh
BAT
, not V
BAT
7
0
DD
TABLE 1. STATUS REGISTER (SR)
. It is a read-only bit and is set/reset by
AL1
6
0
AL0
5
0
DD
, the device sets this bit to “0”.
4
0
0
9
3
0
0
RWEL WEL
2
0
1
0
ISL12024IRTCZ
RTCF
0
1
RWEL: Register Write Enable Latch Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior to any
writes to the Clock/Control Registers. Writes to RWEL bit do
not cause a non-volatile write cycle, so the device is ready
for the next operation immediately after the stop condition. A
write to the CCR requires both the RWEL and WEL bits to be
set in a specific sequence.
WEL: Write Enable Latch - Volatile
The WEL bit controls the access to the CCR during a write
operation. This bit is a volatile latch that powers up in the
LOW (disabled) state. While the WEL bit is LOW, writes to
the CCR address will be ignored, although acknowledgment
is still issued. The WEL bit is set by writing a “1” to the WEL
bit and zeroes to the other bits of the Status Register. Once
set, WEL remains set until either reset to 0 (by writing a “0”
to the WEL bit and zeroes to the other bits of the Status
Register) or until the part powers up again. Writes to WEL bit
do not cause a non-volatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real-Time Clock Fail Bit - Volatile
This bit is set to a ‘1’ after a total power failure. This is a read
only bit that is set internally when the device powers up after
having lost all power to the device. The bit is set regardless
of whether V
of the supplies does not result in setting the RTCF bit. The
first valid write to the RTC after a complete power failure
(writing one byte is sufficient) resets the RTCF bit to ‘0’.
Unused Bits:
Bit 3 in the SR is not used, but must be zero. The Data Byte
output during a SR read will contain a zero in this bit
location.
DD
or V
BAT
is applied first. The loss of only one
August 8, 2008
FN6749.0