M48T59Y-70MH1F STMicroelectronics, M48T59Y-70MH1F Datasheet - Page 10

• Manufacturer Part Number: M48T59Y-70MH1F
• Description: IC TIMEKPR SRAM 64KBIT 5V 28SOIC
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T59Y-70MH1F

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC, 28-SOH (8.48mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4723-2

2.2
Figure 6.
Figure 7.
10/32
A0-A12
E
W
DQ0-DQ7
A0-A12
E
W
DQ0-DQ7
Write mode
The M48T59/Y/V is in the WRITE Mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
prior to the initiation of another READ or WRITE cycle. Data-in must be valid t
the end of WRITE and remain valid for t
WRITE cycles to avoid bus contention; however, if the output bus has been activated by a
low on E and G a low on W will disable the outputs t
Write enable controlled, write mode AC waveforms
Chip enable controlled, write mode AC waveforms
tAVEL
tAVEL
tAVWL
tAVWL
tWLQZ
tAVWH
EHAX
tAVEH
tWLWH
VALID
tAVAV
tAVAV
VALID
tELEH
WHDX
from Chip Enable or t
afterward. G should be kept high during
tDVEH
tDVWH
DATA INPUT
DATA INPUT
WLQZ
tWHDX
after W falls.
WHAX
tEHDX
tWHQX
from WRITE Enable
tEHAX
tWHAX
AI01387B
AI01386
DVWH
prior to