LM9833CCVJD/NOPB National Semiconductor, LM9833CCVJD/NOPB Datasheet - Page 19

• Manufacturer Part Number: LM9833CCVJD/NOPB
• Description: IC USB IMAGE SCAN 48BIT 100-TOFP
• Manufacturer: National Semiconductor

Specifications of LM9833CCVJD/NOPB

• Number Of Bits: 16
• Number Of Channels: 3
• Voltage - Supply, Analog: 5V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: *LM9833CCVJD; *LM9833CCVJD/NOPB; LM9833CCVJD

Register Listing
Address
(NEW)
MISC I/O PIN SETTINGS
5A
59
MISC I/O 1: Input or Output
MISC I/O 1: Polarity
(if configured as an input)
MISC I/O 1: Level/Edge sensitive
(if configured as an input)
MISC I/O 1: Output State
(if configured as an output)
Power On/USB Suspend Default: Input
MISC I/O 2: Input or Output
MISC I/O 2: Polarity
(if configured as an input)
MISC I/O 2: Level/Edge sensitive
(if configured as an input)
MISC I/O 2: Output State
(if configured as an output)
Power On/USB Suspend Default: Input
MISC I/O 3: Input or Output
MISC I/O 3: Polarity
(if configured as an input)
MISC I/O 3: Level/Edge sensitive
(if configured as an input)
MISC I/O 3: Output State
(if configured as an output)
Power On/USB Suspend Default: Input
MISC I/O 4: Input or Output
MISC I/O 4: Polarity
(if configured as an input)
MISC I/O 4: Level/Edge sensitive
(if configured as an input)
MISC I/O 4: Output State
(if configured as an output)
Power On/USB Suspend Default: Output,
Logic High
(Continued)
Function
D
7
0
1
0
1
D
0
1
0
1
6
D
5
0
1
0
1
D
4
0
1
0
1
19
D
0
1
0
1
3
D
2
0
1
0
1
D
1
0
1
0
1
D
0
0 The MISC I/O 1 pin is configured as an input.
1 The MISC I/O 1 pin is configured as an output.
0 The MISC I/O 3 pin is configured as an input.
1 The MISC I/O 3 pin is configured as an output.
A low input on MISC I/O 1 is True
A high input on MISC I/O 1 is True
Level sensitive: MISC I/O 1 State bit (in Status
Register) is set to a 1 if MISC I/O 1 is currently True.
Edge sensitive: MISC I/O 1 State bit (in Status
Register) is set to a 1 if MISC I/O 1 has been True
since the last time the Status Register was read.
The output of the MISC I/O 1 pin will be a logic low
(0V).
The output of the MISC I/O 1 pin will be a logic high
(5V).
The MISC I/O 2 pin is configured as an input.
The MISC I/O 2 pin is configured as an output.
A low input on MISC I/O 2 is True
A high input on MISC I/O 2 is True
Level sensitive: MISC I/O 2 State bit (in Status
Register) is set to a 1 if MISC I/O 2 is currently True.
Edge sensitive: MISC I/O 2 State bit (in Status
Register) is set to a 1 if MISC I/O 2 has been True
since the last time the Status Register was read.
The output of the MISC I/O 2 pin will be a logic low
(0V).
The output of the MISC I/O 2 pin will be a logic high
(5V).
A low input on MISC I/O 3 is True
A high input on MISC I/O 3 is True
Level sensitive: MISC I/O 3 State bit (in Status
Register) is set to a 1 if MISC I/O 3 is currently True.
Edge sensitive: MISC I/O 3 State bit (in Status
Register) is set to a 1 if MISC I/O 3 has been True
since the last time the Status Register was read.
The output of the MISC I/O 3 pin will be a logic low
(0V).
The output of the MISC I/O 3 pin will be a logic high
(5V).
The MISC I/O 4 pin is configured as an input.
The MISC I/O 4 pin is configured as an output.
A low input on MISC I/O 4 is True
A high input on MISC I/O 4 is True
Level sensitive: MISC I/O 4 State bit (in Status
Register) is set to a 1 if MISC I/O 4 is currently True.
Edge sensitive: MISC I/O 4 State bit (in Status
Register) is set to a 1 if MISC I/O 4 has been True
since the last time the Status Register was read.
The output of the MISC I/O 4 pin will be a logic low
(0V).
The output of the MISC I/O 4 pin will be a logic high
(5V).
Value
www.national.com