AD73311LARS Analog Devices Inc, AD73311LARS Datasheet - Page 32

• Manufacturer Part Number: AD73311LARS
• Description: IC ANALOG FRONT END 20-SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73311LARS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 2
• Power (watts): 50mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 20-SSOP

AD73311L
Configuring a Cascade of Two AD73311Ls to Operate in
Data Mode
This section describes the typical sequence of control words that
are required to be sent to a cascade of two AD73311Ls to set
them up for data mode operation. In this sequence Registers B,
C and A are programmed before the device enters data mode.
This description panel refers to Table XXI.
At each sampling event, a pair of SDOFS pulses will be observed
which will cause a pair of control (programming) words to be
sent to the device from the DSP. It is advisable that each pair of
control words should program a single register in each device.
The sequence to be followed is Device 2 followed by Device 1.
In Step 1, we have the first output sample event following device
reset. The SDOFS signal is raised on both devices simultaneously,
which prepares the DSP Rx register to accept the ADC word
from Device 2, while SDOFS from Device 1 becomes an SDIFS
to Device 2. As the SDOFS of Device 2 is coupled to the DSP’s
TFS and RFS, and to the SDIFS of Device 1, this event also
forces a new control word to be output from the DSP Tx regis-
ter to Device 1.
In Step 2, we observe the status of the devices following the
transmission of the first control word. The DSP has received the
output word from Device 2, while Device 2 has received the
output word from Device 1. Device 1 has received the Control
word destined for Device 2. At this stage, the SDOFS of both
devices are again raised because Device 2 has received Device
1’s output word, and as it is not a valid control word addressed
to Device 2, it is passed on to the DSP. Likewise, Device 1 has
received a control word destined for Device 2-address field is
not zero-and it decrements the address field of the control word
and passes it on.
Step 3 shows completion of the first series of control word
writes. The DSP has now received both output words and each
device has received a control word that addresses control register
B and sets the internal MCLK divider ratio to 1, SCLK rate to
DMCLK/2 and sampling rate to DMCLK/256. Note that both
devices are updated simultaneously as both receive the addressed
control word at the same time. This is an important factor in
cascaded operation as any latency between updating the SCLK
or DMCLK of devices can result in corrupted operation. This
will not happen in the case of an FSLB configuration as shown
here, but must be taken into account in a nonFSLB configura-
tion. One other important observation of this sequence is that
the data words are received and transmitted in reverse order,
i.e., the ADC words are received by the DSP, Device 2 first,
then Device 1 and, similarly, the transmit words from the DSP
are sent to Device 2 first, then to Channel 1. This ensures that
all devices are updated at the same time. Steps 4–6 are similar to
1
APPENDIX C
Steps 1–3 but, instead, program Control Register C to power-up
the analog sections of the device (ADCs, DACs and reference).
Steps 7–9 are similar to Steps 1–3 but, instead, program Con-
trol Register A, with a device count field equal to two devices in
cascade and sets the PGM/DATA bit to one to put the device
in data mode.
In Step 10, the programming phase is complete and we now
begin actual device data read and write. The words loaded into
the serial registers of the two devices at the ADC sampling
event now contain valid ADC data and the words written to the
devices from the DSP’s Tx register will now be interpreted as
DAC words. The DSP Tx register contains the DAC word for
Device 2.
In Step 11, the first DAC word has been transmitted into the
cascade and the ADC word from Device 2 has been read from
the cascade. The DSP Tx register now contains the DAC
word for Device 1. As the words being sent to the cascade are
now being interpreted as 16-bit DAC words, the addressing
scheme now changes from one where the address was embed-
ded in the transmitted word, to one where the serial port now
counts the SDIFS pulses. When the number of SDIFS pulses
received equals the value in the Device count field of Control
Register A, the length of the cascade-each device updates its
DAC register with the present word in its serial register. In
Step 11 each device has received only one SDIFS pulse; Device
2 received one SDIFS from the SDOFS of Device 1 when it
sent its ADC word, and Device 1 received one SDIFS pulse
when it received the DAC word for Device 2 from the DSP’s
Tx register. Therefore, each device raises its SDOFS line to
pass on the current word in its serial register, and each device
now receives another SDIFS pulse.
Step 12 shows the completion of an ADC read and DAC write
cycle. Following Step 11, each device has received two SDIFS
pulses that equal the setting of the device count field in Control
Register A. The DAC register in each device is now updated
with the contents of the word that accompanied the SDIFS
pulse that satisfied the device count requirement. The internal
frame sync counter is now reset to zero and will begin counting
for the next DAC update cycle. Steps 10–12 are repeated on
each sampling event.
NOTE
1
This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are
enabled. It is important to ensure that there is no latency (separation) between
control words in a cascade configuration. This is especially the case when
programming Control Registers A and B, as they must be updated synchro-
nously in each channel.