LM9832CCVJD National Semiconductor, LM9832CCVJD Datasheet - Page 10

• Manufacturer Part Number: LM9832CCVJD
• Description: IC SCANNER CLR USB IMAGE 100TQFP
• Manufacturer: National Semiconductor

Specifications of LM9832CCVJD

• Number Of Bits: 14
• Number Of Channels: 3
• Voltage - Supply, Analog: 5V
• Voltage - Supply, Digital: 5V
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Other names: *LM9832CCVJD

Register Listing
Registers in bold boxes are reset to that value on power-up. All register addresses are in hexadecimal. All other numbers are
decimal unless otherwise noted.
Address
IMAGE BUFFER (READ ONLY)
STATUS REGISTERS (READ ONLY)
DATAPORT REGISTERS
00
01
02
03
04
05
06
Pixel (Image) Data
Image Data Available In Buffer
PAPER SENSE 1 State
read clears bit if edge sensitive input.
PAPER SENSE 2 State
read clears bit if edge sensitive input.
MISC I/O 1 State
read clears bit if edge sensitive input.
MISC I/O 2 State
read clears bit if edge sensitive input.
MISC I/O 3 State
read clears bit if edge sensitive input.
MISC I/O 4 State
read clears bit if edge sensitive input.
MISC I/O 5 State
read clears bit if edge sensitive input.
MISC I/O 6 State
read clears bit if edge sensitive input.
DataPort Target
DataPort Target Color
Pause (Read Only)
This bit indicates whether or not the scanner
is currently paused due to a buffer full
condition.
DRAM Test
DataPort Address - MSB
DataPort Address - LSB
DataPort
Function
D
7
n n n n n n n n One byte of image data.
n n n n n n n n
0
1
a a a a a a a a
n n n n n n n n
D
6
0
1
0
1
R
/
W
D
0
1
a a a a a a
5
D
0
1
0
1
4
10
D
3
0
1
0 0
0 1
1 0
1 1
D
0
1
2
D
0
1
0 0 Offset Coefficient Data
0 1 Gain Coefficient Data
1 0 Gamma Lookup Table
1 1 N/A
1
D
0
0 False
1 True
n*2 (256k x 16 DRAM) or n*8 (1M x 16 DRAM)
kilobytes of image data is available
False
True
False
True
False
True
False
True
False
True
False
True
False
True
Red
Green
Blue
N/A
Normal State
The scanner is currently in the pause/reverse cycle.
Normal Operation
DRAM Test mode
Address of location to be read/written to.
a = 0 to 4095 for gamma tables,
0 to 16383 for Offset and Gain Coefficient Data
Addresses greater than these are illegal.
Bit D6 of register 4 indicates whether next operation
will be a Read (D6=1) or a Write (D6=0).
Data to be read from or written to the address of the
currently selected Dataport Target. The DataPort
Address is automatically incremented whenever one
(gamma data) or two (Gain/Offset Data) bytes are
read from or written to this register.
Value
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