LM9832CCVJD National Semiconductor, LM9832CCVJD Datasheet - Page 37

• Manufacturer Part Number: LM9832CCVJD
• Description: IC SCANNER CLR USB IMAGE 100TQFP
• Manufacturer: National Semiconductor

Specifications of LM9832CCVJD

• Number Of Bits: 14
• Number Of Channels: 3
• Voltage - Supply, Analog: 5V
• Voltage - Supply, Digital: 5V
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Other names: *LM9832CCVJD

Applications Information
transmitted to the dataport as:
0003: 0000 0000 0000 1100
0031: 0000 0000 0111 1100
4096: 0100 0000 0000 0000
13.1.5 Pixel Rate Shading Multiplier
The shading multiplier uses all 16 bits of data.
There is an important difference between the pixel rate shading
multiplier of the LM9830 and the LM9832. In the LM9830, if the
value for the shading multiplier was 0, the gain through the multi-
plier was 1V/V. The LM9830 also had 3 multiplier gain ranges: 1
to 1.5, 1 to 2.0, and 1 to 3.0 V/V.
The LM9832 has a simpler multiplier with only one gain range: 0
to 4 V/V. The gain of the multiplier is
Note that if the gain code = 0, then the pixel is multiplied by 0! In
other words, if the gain coefficient is set to 0, the output of the
multiplier will be all 0s. A gain code of 0 was not unusual for the
LM9830, but will not work with the LM9832. To maintain a mini-
mum gain of 1V/V, make sure the gain code is 16384 or higher.
If desired, gains between 0 and 1 V/V can be used, but they will
usually result in less dynamic range and noisier images.
13.1.6 The Gamma Table
The LM9832’s 3 gamma tables are 12 bits wide, instead of 10 bits
(LM9830). This means each gamma curve has 4 times the num-
ber of datapoints and you can now get 4 times the accuracy avail-
able with the LM9830.
Since most consumer CCDs have a true SNR of less than 12 bits,
the LM9832 does not support a 14 bit gamma table, freeing up an
additional 36kwords of DRAM memory.
13.1.7 General DataPort Information
There have been several important changes to the dataport.
The read-only Pause bit is now in register 3. You can write this bit
in order to write to the other bits in the register, but anything you
write to the Pause bit will be ignored.
There are now 2 bits to select between Offset Coefficients, Gain
Coefficients, and Gamma data.
In the LM9830, Offset and Gain coefficients were combined to
make one 16 bit word, written to register 6 as 2 bytes.
In the LM9832, Offset is a 16 bit word, and Gain is a 16 bit word.
Offset and Gain data each have a separate dataport address.
Register 5 will auto increment after 2 bytes are written to register
6 in Offset mode or Gain mode (reg03b1 = 0).
Gamma data is 8 bits wide, as in the LM9830. Register 5 will auto
increment after 1 gamma byte is written to register 6 in Gamma
mode (reg03b1 = 1).
The bit locations for selecting color (R, G, or B), have been
shifted left by 1 bit.
The DataPort address width is now 14 bits wide. This caused the
R/W bit to be shifted left by 1 bit.
When using 1 Channel Grayscale, the LM9830 ignored the color
bits in register 3. This has been fixed in the LM9832. Register 3
controls the gamma table color.
Gain = (gain code)/16384 V/V
(Continued)
37
Make sure your software takes all of these changes into account.
13.2 Porting Step 2
Once your TWAIN driver is operating with the LM9832, you can
start taking advantage of the LM9832’s additional features.
13.2.1 1200 DPI
The LM9832 can support line widths up to 16384 pixels x 3 col-
ors. This allows 1200dpi scanners with a maximum width of 13.6”
(B-size).
13.2.2 Integration Time Adjustment Function
Due to DRAM speed limitations, the maximum speed at which the
LM9832 can store pixels is 1MHz. The ADC can run at speeds up
to 6MHz, but only when the HDPI divider is set to divide-by-6 or
greater, which results in a pixel rate of 1MHz or less.
This can be a challenge when scanning at high resolutions. For
example, a 600dpi 8.5” wide color CCD scanner digitizes 15,300
pixels/line. At a 1MHz rate, the resulting integration time
is15.3ms. Integration times above 10ms may be problematic in
some designs.
To allow shorter integration times without violating the 1MHz max
pixel rate, the LM9832 has an Integration Time Adjust (ITA) func-
tion (Figure 47). ITA generates 2 alternating timebases for the
CCD timing, a high frequency timebase, and a lower frequency
timebase. During the high frequency timebase, the integration
time (t
divided by 6MHz. (Using the previous example, that would be
2.5ms). During t
digitized by the AFE. The CCD output signal (representing line “n-
1”) is discarded.
After the short integration time, the clock is slowed for the next
integration time (t
this period. Since t
pixel data for line “n”. As long as t
of 1MHz or slower, the line can be digitized and written to the
DRAM.
t
MCLK divider and line end settings. t
There are two more considerations when using the ITA. The first
is CCD image lag. Image lag is a sensor phenomenon in which a
percentage of the pixel voltage from the previous line appears in
the pixel voltage for the current line. In the example above, some
of the signal from line n-1 will leak into line n. Since the integra-
tion time for line n-1 (t
leakage may be as much as 2 to 6 times the sensor specified
image lag. This is usually not a problem. If it is, use a sensor with
a low image lag specification, or reduce the brightness of the
INT 1
Pixel
Data
TR
is determined by the traditional calculations, primarily the
INT1
) is short, as short as the total number of pixels in a line
Figure 47: Integration Time Adjust Function
line n-2
line n-1
INT1
t
INT2
INT2
INT2
, data is clocked out of the CCD but it is not
= ITA * t
). Integration for line “n+1” is done during
INT2
discard
is longer, there is more time to read out
line n
t
INT1
) is 2 to 6 times longer than t
INT1
INT2
INT2
corresponds to a pixel rate
line n+1
= ITA * t
t
line n
INT2
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INT1
.
INT1
, the