AD7888ARZ Analog Devices Inc, AD7888ARZ Datasheet - Page 4

• Manufacturer Part Number: AD7888ARZ
• Description: IC ADC 12BIT 8CH SRL 16-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7888ARZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 125k
• Number Of Converters: 1
• Power Dissipation (max): 3.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 125kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 700µA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
AD7888
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
Specifications subject to change without notice.
SCLK
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/Space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section.
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
t
CONVERT
ACQ
1
2
3
4
5
6
7
8
9
cross 0.4 V or 2.0 V with V
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
8
3
3
4
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
2
4.75 V to 5.25 V
2
14.5 t
1.5 t
10
30
75
20
20
0.4 t
0.4 t
80
5
DD
SCLK
SCLK
SCLK
= 3 V ± 10%.
SCLK
Limit at T
(A, B Versions)
1
(T
MIN
A
2.7 V to 3.6 V
2
14.5 t
1.5 t
10
60
100
20
20
0.4 t
0.4 t
80
5
= T
, T
MIN
OUTPUT
MAX
SCLK
SCLK
SCLK
SCLK
to T
PIN
TO
MAX
50pF
, unless otherwise noted)
C
L
Unit
MHz max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs typ
200 A
200 A
I
I
OH
OL
Description
Throughput Time = t
CS to SCLK Setup Time
Delay from CS until DOUT 3-State Disabled
Data Access Time after SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
Data Valid to SCLK Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to DOUT High Impedance
Power-Up Time from Shutdown
8
, quoted in the timing characteristics is the true bus relinquish
1.6V
DD
) and timed from a voltage level of 1.6 V.
DD
CONVERT
= 5 V ± 10% and time for an output to
+ t
ACQ
= 16 t
SCLK
REV. C