AD1871YRSZ Analog Devices Inc, AD1871YRSZ Datasheet - Page 7

• Manufacturer Part Number: AD1871YRSZ
• Description: IC ADC STEREO AUDIO 24BIT 28SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD1871YRSZ

• Data Interface: Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 96k
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Supply Current: 40mA
• Digital Ic Case Style: SSOP
• Number Of Elements: 2
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 96KSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±2.828V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DATA INTERFACE TIMING (CASCADE MODE–MASTER)
Mnemonic
t
t
t
t
t
t
DATA INTERFACE TIMING (CASCADE MODE–SLAVE)
Mnemonic
t
t
t
t
t
t
t
DATA INTERFACE TIMING (MODULATOR MODE)
Mnemonic
t
t
t
t
t
t
REV. 0
BCHDC
BCLDC
BLRDC
BDDC
BDIS
BDIH
BCHC
BCLC
BDSDC
LRSC
LRHC
BDIS
BDIH
MOCH
MOCL
MHDD
MLDD
MMDR
MMDF
BCLK High Delay
BCLK Low Delay
LRCLK Delay
DOUT Delay
DIN Setup
DIN Hold
BCLK High Width
BCLK Low Width
DOUT Delay
LRCLK Setup
LRCLK Hold
DIN Setup
DIN Hold
MODCLK High Width
MODCLK Low Width
MOD DATA High Delay
MOD DATA Low Delay
MODCLK Delay Rising
MODCLK Delay Falling
Description
Description
Description
Figure 4. Master Cascade Interface Timing
Figure 5. Slave Cascade Interface Timing
LRCLK
LRCLK
DOU T
DOU T
M CLK
BCLK
BCLK
M ODCLK
D[0 – 3 ]
Figure 6. Modulator Mode Timing
Min
20
20
10
10
10
10
Min
20
10
5
10
10
Min
t
BCH DC
t
t
Typ
Typ
Typ
20
30
20
30
30
LRSC
MCLK
MCLK
30
BLRDC
t
LRH C
t
t
M LDD
–7–
t
BDSDC
t
t
BDDC
BCLDC
M H DD
Max
Max
Max
t
BCH C
t
M OCH
t
BCLC
t
M OCL
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comment
From MCLK Rising
From MCLK Falling
From BCLK Rising
From BCLK Rising
To BCLK Rising
From BCLK Rising
Comment
From BCLK Rising
To BCLK Rising
From BCLK Rising
To BCLK Rising
From BCLK Rising
Comment
From MCLK Rising
From MCLK Falling
MCLK Falling to MODCLK Rising
MCLK Falling to MODCLK Falling
AD1871