AD1871YRSZ Analog Devices Inc, AD1871YRSZ Datasheet - Page 8

• Manufacturer Part Number: AD1871YRSZ
• Description: IC ADC STEREO AUDIO 24BIT 28SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD1871YRSZ

• Data Interface: Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 96k
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Supply Current: 40mA
• Digital Ic Case Style: SSOP
• Number Of Elements: 2
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 96KSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±2.828V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD1871
CONTROL INTERFACE (SPI) TIMING
Mnemonic
t
t
t
t
t
t
t
t
t
t
DIGITAL I/O
Parameter
Input Voltage High (V
Input Voltage Low (V
Input Leakage (I
Input Leakage (I
Output Voltage High (V
Output Voltage Low (V
Input Capacitance
POWER
Parameter
Supplies
*RESET held low.
TEMPERATURE RANGE
Parameter
Specifications Guaranteed
Functionality Guaranteed
Storage
Specifications subject to change without notice.
CCH
CCL
CCP
CDS
CDH
CLS
CLH
COE
COD
COTS
Voltage, AVDD, and DVDD
Voltage, ODVDD
Analog Current
Analog Current—Power-Down (MCLK Running)
Digital Current, DVDD
Digital Current, ODVDD
Digital Current—Power-Down (MCLK Running) DVDD*
Digital Current—Power-Down (MCLK Running) ODVDD*
Power Supply Rejection
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
IH
IL
Description
CCLK High Width
CCLK Low Width
CCLK Period
CDATA Setup Time
CDATA Hold Time
CLATCH Setup Time
CLATCH Hold Time
COUT Enable
COUT Delay
COUT Three-State
@ V
@ V
CLATCH
CCLK
COUT
IL
IH
CIN
IL
)
IH
OL
OH
)
= 0 V)
= 5 V)
@ I
@ I
OL
D15
OH
= +2 mA)
= –2 mA)
D14
t
CCH
t
CCL
D13
D12
Figure 7. Control Interface Timing
D11
Min
40
40
80
10
10
10
10
15
20
25
D10
Min
–40
–65
t
CSU
D09
D09
Typ
D08
D08
–8–
Min
2.4
ODVDD – 0.4 V
D07
D07
t
CHD
t
CCL
Max
D06
D06
Min
4.5
2.7
D05
D05
Typ
25
D04
D04
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D03
D03
Typ
Typ
5
40
4.0
18
0.5
0.8
1.0
–86
–77
D02
D02
Comment
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Rising
From CLATCH Falling
From CCLK Falling
From CLATCH Rising
D01
D01
D00
D00
Max
+105
+150
Max
5.5
5.5
45
6.0
22
1.0
2.0
15.0
Max
0.8
10
10
0.4
15
t
CLH
REV. 0
Unit
V
V
mA
mA
V
V
pF
Unit
V
V
mA
mA
mA
mA
mA
mA
dB
dB
Unit
∞C
∞C
∞C