AD7730BRZ Analog Devices Inc, AD7730BRZ Datasheet - Page 27

• Manufacturer Part Number: AD7730BRZ
• Description: IC ADC BRIDGE TRANSDUCER 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7730BRZ

• Data Interface: DSP, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 1.2k
• Number Of Converters: 1
• Power Dissipation (max): 125mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Resolution (bits): 24bit
• Sampling Rate: 1.2kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Package: 24SOIC W
• Resolution: 24 Bit
• Architecture: Delta-Sigma
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial (3-Wire, SPI)
• Input Type: Voltage
• Signal To Noise Ratio: 123 dB
• Polarity Of Input Voltage: Unipolar|Bipolar
• Number Of Elements: 1
• Sample Rate: 1.2KSPS
• Input Polarity: Unipolar/Bipolar
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 125mW
• Integral Nonlinearity Error: 18ppm of FSR
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: SOIC W
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7730LEBZ - BOARD EVALUATION FOR AD7730EVAL-AD7730EBZ - BOARD EVAL FOR AD7730
• Lead Free Status / Rohs Status: Compliant

Chop Mode
With chop mode enabled on the AD7730, the signal processing
chain is synchronously chopped at the analog input and at the
output of the first stage filter. This means that for each output
of the first stage filter to be computed, the full settling time of
the filter has to elapse. This results in an output rate from the
filter that is three times lower than for a given SF word than for
nonchop mode. The output update and first notch of this first
stage filter correspond and are determined by the relationship:
where SF is the decimal equivalent of the data loaded to the SF
bits of the Filter Register and f
Second Stage Filter
As stated earlier, the second stage filter has three distinct modes
of operation which result in a different overall filter profile for
the part. The modes of operation of the second stage filter are
discussed in the following sections along with the different filter
profiles which result.
Normal FIR Operation
The normal mode of operation of the second stage filter is as a
22-tap low-pass FIR filter. This second stage filter processes the
output of the first stage filter and the net frequency response of
the filter is simply a product of the filter response of both filters.
The overall filter response of the AD7730 is guaranteed to have
no overshoot.
Figure 11 shows the full frequency response of the AD7730 when
the second stage filter is set for normal FIR operation. This
response is for chop mode enabled with the decimal equivalent
of the word in the SF bits set to 512 and a master clock frequency
of 4.9152 MHz. The response will scale proportionately with
master clock frequency. The response is shown from dc to
100 Hz. The rejection at 50 Hz 1 Hz and 60 Hz
better than 88 dB.
The –3 dB frequency for the frequency response of the AD7730
with the second stage filter set for normal FIR operation and
chop mode enabled is determined by the following relationship:
In this case, f
tion is greater than 64.5 dB, is determined by:
In this case, f
REV. A
3 dB
STOP
f
Output Rate
f
3 dB
= 7.9 Hz and the stopband, where the attenua-
STOP
= 28 Hz.
0.0395
0.14
CLK IN
f
f
CLK IN
f
CLK IN
16
CLK IN
16
16
is the master clock frequency.
3 SF
3 SF
3 SF
1
1
1
1 Hz is
–27–
Figure 11. Detailed Full Frequency Response of AD7730
(Second Stage Filter as Normal FIR, Chop Enabled)
Figure 12 shows the frequency response for the same set of
conditions as for Figure 11, but in this case the response is
shown out to 600 Hz. This response shows that the attenuation
of input frequencies close to 200 Hz and 400 Hz is significantly
less than at other input frequencies. These “peaks” in the fre-
quency response are a by-product of the chopping of the input.
The plot of Figure 12 is the amplitude for different input fre-
quencies. Note that because the output rate is 200 Hz for the
conditions under which Figure 12 is plotted, if something ex-
isted in the input frequency domain at 200 Hz, it would be
aliased and appear in the output frequency domain at dc.
Figure 12. Expanded Full Frequency Response of AD7730
(Second Stage Filter as Normal FIR, Chop Enabled)
–100
–110
–120
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
0
50 100 150 200 250 300 350 400
10
20
30
FREQUENCY – Hz
FREQUENCY – Hz
40
AD7730/AD7730L
50
60
70
450
80
500 550 600
90
100