KAD5512P-50Q72 Intersil, KAD5512P-50Q72 Datasheet

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... These adjustments allow the user to minimize spurs associated with the interleaving process. Digital output data is presented in selectable LVDS or CMOS formats. The KAD5512P-50 is available in a 72-contact QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40°C to +85°C). ...

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... Ordering Information PART NUMBER (Note) KAD5512P-50Q72 KAD5512P-50 Q72EP-I NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...

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... Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . 14 User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Jitter Voltage Reference Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Over Range Indicator . . . . . . . . . . . . . . . . . . . . . . . . . .17 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 KAD5512P-50 Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . 20 SPI Physical Interface SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Indexed Device Configuration/Control . . . . . . . . . . . . 21 Global Device Configuration/Control Device Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI Memory Map ...

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... P-P P 3mA LVDS CSB at logic high D Sample Clock Running Sample Clock Running DNL INL f MIN S f MAX S = -1dBFS 500MSPS. SAMPLE KAD5512P-50 (Note 2) MIN TYP MAX 1.40 1.47 1.54 500 1.9 90 -10.0 ±2.0 10.0 ±2.0 435 535 635 0.9 1.8 1.7 1.8 1 ...

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... 190MHz 364MHz 695MHz 995MHz IN IMD f = 70MHz 170MHz IN WER FPBW OVDD = -1dBFS 500MSPS. (Continued) SAMPLE KAD5512P-50 (Note 2) MIN TYP MAX 65.9 63.6 65.9 65.8 65.5 64.4 63.2 65.7 63.2 65.7 65.7 65.0 59.8 50.0 10.6 10.2 10.6 10.6 10.5 9.7 8.0 87 ...

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... Output Rise Time Output Fall Time Timing Diagrams SAMPLE N INP INN t A CLKN CLKP LATENCY = L CYCLES t CPD CLKOUTN CLKOUTP D[11:0]P DATA DATA N-L N-L+1 D[11:0]N FIGURE 1. LVDS TIMING DIAGRAM (see “Digital Outputs” on page 17) 6 KAD5512P-50 CONDITIONS MIN 3mA Mode ...

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... SPI Interface timing is directly proportional to the ADC sample period (t 11. The SPI may operate asynchronously with respect to the ADC sample clock. 12. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time (4ns min). 7 KAD5512P-50 CONDITION SYMBOL t A ...

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... RLVDS 47 CLKOUTN 48 CLKOUTP [CLKOUT KAD5512P-50 AVDD 1.8V Analog Supply DNC Do Not Connect AVSS Analog Ground Analog Input Negative, Positive VCM Common Mode Output Tri-Level Clock Divider Control Clock Input True, Complement Tri-Level Output Mode (LVDS, LVCMOS) Tri-Level Power Control (Nap, Sleep modes) Power-On Reset (Active Low, see “ ...

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... OUTFMT Exposed Paddle NOTE: LVCMOS Output Mode Functionality is shown in brackets ( Connection) 9 KAD5512P-50 D7N LVDS Bit 7 Output Complement [NC] [NC in LVCMOS] D7P LVDS Bit 7 Output True [D7] [LVCMOS Bit 7] D8N LVDS Bit 8 Output Complement [NC] [NC in LVCMOS] D8P LVDS Bit 8 Output True [D8] [LVCMOS Bit 8] D9N ...

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... Pinout AVDD 1 DNC 2 3 DNC 4 DNC 5 DNC 6 AVDD 7 AVSS 8 AVSS 9 VINN 10 VINP 11 AVSS 12 AVDD 13 DNC 14 DNC 15 VCM 16 CLKDIV 17 DNC DNC KAD5512P-50 KAD5512P-50 (72 LD QFN) TOP VIEW CONNECT THERMAL PAD TO AVSS D8P 53 D8N 52 D7P 51 D7N 50 D6P 49 D6N 48 CLKOUTP 47 CLKOUTN 46 RLVDS 45 OVSS 44 D5P ...

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... SFDR SNR 65 60 300 325 350 375 400 SAMPLE RATE (MSPS) FIGURE 7. SNR AND SFDR KAD5512P-50 All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V 500MSPS. SAMPLE -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 600M 800M ...

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... CODE FIGURE 13. NOISE HISTOGRAM 12 KAD5512P-50 All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V 500MSPS. (Continued) SAMPLE 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0 ...

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... SNR = 61.2dBFS SFDR = 49.6dBc -20 SINAD = 50.0dBFS -40 -60 -80 -100 -120 0M 50M 100M FREQUENCY (Hz) FIGURE 17. SINGLE-TONE SPECTRUM @ 995MHz 13 KAD5512P-50 All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V 500MSPS. (Continued) SAMPLE 0 -20 -40 -60 -80 -100 -120 0M 150M 200M 250M FIGURE 16 ...

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... The KAD5512P-50 does not have the ability to adjust timing skew mismatches as part of the internal calibration sequence. Clock routing to each unit ADC is carefully matched, however ...

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... OVDD the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the KAD5512P-50 changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements ...

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... VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5512P-50 is 500Ω. The SHA design uses a switched capacitor input stage (see Figure 40), which creates current spikes when the sampling capacitance is reconnected to the input voltage ...

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... The OR bit is updated at the sample rate. Power Dissipation The power dissipated by the KAD5512P-50 is primarily dependent on the sample rate and the output modes: LVDS vs. CMOS and DDR vs. SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate ...

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... XOR of the current bit position and the next most significant bit. Figure 30 shows this operation. 18 KAD5512P-50 GRAY CODE FIGURE 30. BINARY TO GRAY CODE CONVERSION Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 31 ...

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... W1 W0 CSB SCLK SDIO DSW CSB t S SCLK SDIO R DSW CSB t S SCLK SDIO R A12 SDO 19 KAD5512P-50 A12 A11 A10 FIGURE 32. MSB-FIRST ADDRESSING A11 A12 W0 W1 R/W D0 FIGURE 33. LSB-FIRST ADDRESSING t t CLK HI t DHW t LO A12 A11 A10 SPI WRITE FIGURE 34. SPI WRITE ...

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... The SPI port operates in a half duplex master/slave configuration, with the KAD5512P-50 functioning as a slave. Multiple slave devices can interface to a single master in three-wire mode only, since the SDO output of an unaddressed device is asserted in four wire mode ...

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... Device Information ADDRESS 0X08: CHIP_ID ADDRESS 0X09: CHIP_VERSION The generic die identifier and a revision number, respectively, can be read from these two registers. 21 KAD5512P-50 Indexed Device Configuration/Control ADDRESS 0X10: DEVICE_INDEX_A Bits 1:0 ADC01, ADC00 Determines which ADC is addressed. Valid states for this 1 register are 0x01 or 0x10 ...

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... FIGURE 38. PHASE SLIP: CLK÷2 MODE, f Sleep Mode ADDRESS 0X72: CLOCK_DIVIDE The KAD5512P-50 has a selectable clock divider that can be set to divide by two or one (no division). By default, the tri-level CLKDIV pin selects the divisor (refer to “Clock Input” on page 16). This functionality can be overridden and controlled through the SPI, as shown in Table 12 ...

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... ADDRESS 0X73: OUTPUT_MODE_A The output_mode_A register controls the physical output format of the data, as well as the logical coding. The KAD5512P-50 can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or low (2mA). By default, the tri-level OUTMODE pin selects the mode and drive level (refer to “ ...

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... These registers define the lower and upper eight bits, respectively, of the first user-defined test word. ADDRESS 0XC4: USER_PATT2_LSB ADDRESS 0XC5: USER_PATT2_MSB These registers define the lower and upper eight bits, respectively, of the second user-defined test word. 24 KAD5512P-50 WORD 1 WORD 2 N/A N/A N/A N/A ...

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... Output Mode [2:0] 000 = Pin Control 001 = LVDS 2mA 010 = LVDS 3mA 100 = LVCMOS other codes = reserved 74 output_mode_B 75 config_status 76-BF reserved 25 KAD5512P-50 TABLE 17. SPI MEMORY MAP BIT 6 BIT 5 BIT 4 BIT 3 LSB Soft First Reset Reserved Burst end address [7:0] Reserved Chip ID # ...

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... CSAMP 1.6pF INP Φ Φ 500O Ω CSAMP AVDD 1.6pF INN Φ Φ FIGURE 40. ANALOG INPUTS 26 KAD5512P-50 TABLE 17. SPI MEMORY MAP (Continued) BIT 6 BIT 5 BIT 4 BIT 3 Output Test Mode [3: Off 1 = Midscale Short 2 = +FS Short 3 = -FS Short 4 = Checker Board 5 = reserved 6 = reserved Reserved B6 ...

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... FPGA based data capture motherboard and a family of ADC daughtercards. This USB based platform allows a user to quickly evaluate the ADC’s performance at a user’s specific application frequency requirements. More information is available at http://www.intersil.com/converters/adc_eval_platform/ 27 KAD5512P-50 AVDD (20k PULL-UP ON RESETN ONLY) TO SENSE ...

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... Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. 28 KAD5512P-50 Effective Number of Bits (ENOB alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full- scale voltage less 2 LSB ...

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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 29 KAD5512P-50 CHANGE FN6805.3 October 9, 2009 ...

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... Package Outline Drawing L72.10x10D 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08 10.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 9.80 Sq 6.00 Sq TYPICAL RECOMMENDED LAND PATTERN 30 KAD5512P- 10. 72X 0.40 BOTTOM VIEW 0.90 Max 68X 0.50 72X 0. REF C 72X 0.60 NOTES: 1. Dimensions are in millimeters. ...