KAD5512P-21Q72 Intersil, KAD5512P-21Q72 Datasheet
KAD5512P-21Q72
Specifications of KAD5512P-21Q72
Related parts for KAD5512P-21Q72
KAD5512P-21Q72 Summary of contents
Page 1
... Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates 250MSPS. The KAD5512P is part of a pin-compatible portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging from 125MSPS to 500MSPS. A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset ...
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... DNC 6 AVDD 7 AVSS AVSS 8 9 VINN 10 VINP 11 AVSS 12 AVDD 13 DNC 14 DNC 15 VCM 16 CLKDIV 17 DNC DNC KAD5512P RESOLUTION KAD5512P (72 LD QFN) TOP VIEW PAD CONNECT THERMAL PAD TO AVSS FIGURE 1. PIN CONFIGURATION PACKAGE SPEED (MSPS) Q48EP 250/210/170/125 X 500 250/210/170/125 X 250/210/170/125 X 500 250/210/170/125 X 60 ...
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... RLVDS 47 CLKOUTN [NC] 48 CLKOUTP [CLKOUT] 49 D6N [NC] 3 KAD5512P LVDS [LVCMOS] FUNCTION SDR MODE 1.8V Analog Supply Do Not Connect Analog Ground Analog Input Negative, Positive Common Mode Output Tri-Level Clock Divider Control Clock Input True, Complement Tri-Level Output Mode Control (LVDS, LVCMOS) ...
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... OUTFMT PAD AVSS (Exposed Paddle) NOTE: LVCMOS Output Mode Functionality is shown in brackets ( Connection). SDR is the default state at power-up for the 72 pin package. 4 KAD5512P (Continued) LVDS [LVCMOS] FUNCTION SDR MODE LVDS Bit 6 Output True [LVCMOS Bit 6] LVDS Bit 7 Output Complement [NC in LVCMOS] ...
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... Pin Configuration AVDD 1 DNC 2 3 DNC 4 DNC AVSS 5 6 VINN 7 VINP 8 AVSS AVDD 9 VCM 10 DNC 11 AVSS 12 5 KAD5512P KAD5512P (48 LD QFN) TOP VIEW PAD CONNECT THERMAL PAD TO AVSS FIGURE 2. PIN CONFIGURATION D4P 35 D4N 34 D3P 33 D3N 32 CLKOUTP 31 CLKOUTN 30 RLVDS 29 OVSS 28 D2P 27 D2N ...
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... PAD (Exposed Paddle) NOTE: LVCMOS Output Mode Functionality is shown in brackets ( Connection). 6 KAD5512P AVDD 1.8V Analog Supply DNC Do Not Connect AVSS Analog Ground Analog Input Negative, Positive VCM Common Mode Output Clock Input True, Complement Tri-Level Power Control (Nap, Sleep modes) Power On Reset (Active Low, see page 19) ...
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... Ordering Information PART NUMBER (Note 3) KAD5512P-25Q72 (Note 1) KAD5512P-25 Q72EP-I KAD5512P-21Q72 (Note 1) KAD5512P-21 Q72EP-I KAD5512P-17Q72 (Note 1) KAD5512P-17 Q72EP-I KAD5512P-12Q72 (Note 1) KAD5512P-12 Q72EP-I KAD5512P-25Q48 (Note 2) KAD5512P-25 Q48EP-I KAD5512P-21Q48 (Note 2) KAD5512P-21 Q48EP-I KAD5512P-17Q48 (Note 2) KAD5512P-17 Q48EP-I KAD5512P-12Q48 (Note 2) KAD5512P-12 Q48EP-I NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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... Clock Input ................................................... 20 Jitter ............................................................ 20 Voltage Reference .......................................... 21 Digital Outputs .............................................. 21 Over Range Indicator...................................... 21 Power Dissipation........................................... 21 Nap/Sleep ..................................................... 21 Data Format .................................................. 22 8 KAD5512P Serial Peripheral Interface .............................. 24 SPI Physical Interface .................................... 24 SPI Configuration .......................................... 24 Device Information ........................................ 25 Indexed Device Configuration/Control .............. 25 Global Device Configuration/Control ................. 26 Device Test................................................... 27 72 Pin/48 Pin Package Options ........................ 27 SPI Memory Map ........................................... 28 Equivalent Circuits ...
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... -1dBFS, IN KAD5512P-17 KAD5512P-12 (Note 6) (Note 6) TYP MAX MIN TYP MAX 1000 1000 1.8 1 -10 ±2 10 -10 ±2 ±0.6 ±0.6 635 435 535 635 ...
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... IN KAD5512P-17 KAD5512P-12 (Note 6) (Note 6) TYP MAX MIN TYP MAX -36 -36 271 237 253 219 204 189 ...
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... IN KAD5512P-17 KAD5512P-12 (Note 6) (Note 6) TYP MAX MIN TYP MAX 65.8 66.3 64.3 65.8 64.3 66.3 65.5 65.6 64.7 64.1 57.9 57.4 48.3 49.3 10.6 10.7 10.5 10.6 10 ...
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... Input Current Low (OUTMODE, NAPSLP, CLKDIV, OUTFMT) Input Capacitance LVDS OUTPUTS Differential Output Voltage Output Offset Voltage Output Rise Time Output Fall Time CMOS OUTPUTS Voltage Output High Voltage Output Low Output Rise Time Output Fall Time 12 KAD5512P SYMBOL CONDITIONS MIN 1. ...
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... PD D[10/8/6/4/2/0] ODD BITS EVEN BITS ODD BITS EVEN BITS N-L N FIGURE 4A. DDR FIGURE 4. CMOS TIMING DIAGRAM (See “Digital Outputs” on page 21) 13 KAD5512P CLKOUTN CLKOUTP D[11/0]P ODD BITS EVEN BITS EVEN BITS N N D[11/0]N INP INN CLKN CLKP ...
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... SPI Interface timing is directly proportional to the ADC sample period (4ns at 250Msps). 13. The SPI may operate asynchronously with respect to the ADC sample clock. 14. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time (4ns min). 14 KAD5512P CONDITION SYMBOL t A ...
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... FIGURE 7. SNR AND SFDR SFDR SNR 100 130 160 SAMPLE RATE (MSPS) FIGURE 9. SNR AND SFDR KAD5512P All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V -1dBFS (per speed grade). -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 ...
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... CODE FIGURE 15. NOISE HISTOGRAM 16 KAD5512P All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V -1dBFS (per speed grade). (Continued) 1.5 1.0 0.5 0 DDR -0.5 -1.0 -1 ...
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... FREQUENCY (MHz) FIGURE 19. SINGLE-TONE SPECTRUM @ 495MHz 0 -20 -40 -60 -80 -100 -120 FREQUENCY (MHz) FIGURE 21. TWO-TONE SPECTRUM @ 70MHz 17 KAD5512P All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V -1dBFS 105MHz (per speed grade). (Continued) 0 -20 -40 -60 -80 -100 -120 ...
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... Theory of Operation Functional Description The KAD5512P is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 23). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges ...
Page 19
... As is the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the KAD5512P changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements ...
Page 20
... This dual transformer scheme is used to improve common- mode rejection, which keeps the common-mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5512P is 1000Ω. ADT1-1WT ADT1-1WT 1000pF FIGURE 28. TRANSFORMER INPUT FOR GENERAL ...
Page 21
... The OR bit is updated at the sample rate. Power Dissipation The power dissipated by the KAD5512P is primarily dependent on the sample rate and the output modes: LVDS vs. CMOS and DDR vs SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate ...
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... Scale 111 11 111 KAD5512P Offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two’s complement coding simply complements the MSB of the offset binary representation. ...
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... SCLK SDIO DSW CSB t S SCLK SDIO R DSW CSB t S SCLK SDIO R SDO CSB SCLK SDIO INSTRUCTION/ADDRESS 23 KAD5512P A12 A11 A10 FIGURE 35. MSB-FIRST ADDRESSING A11 A12 W0 W1 R/W D0 FIGURE 36. LSB-FIRST ADDRESSING t t CLK HI t DHW t LO A12 A11 A10 SPI WRITE FIGURE 37 ...
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... If the 4.7kΩ resistor is not present the ADC will not exit the reset state. The SPI port operates in a half duplex master/slave configuration, with the KAD5512P functioning as a slave. Multiple slave devices can interface to a single master in three-wire mode only, since the SDO output of an unaddressed device is asserted in four-wire mode ...
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... The input offset of the ADC core can be adjusted in fine and coarse steps. Both adjustments are made via an 8- bit word as detailed in Table 7. 25 KAD5512P The default value of each register will be the result of the self-calibration after initial power-up register incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register ...
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... Normal Operation Nap Mode ADDRESS 0X72: CLOCK_DIVIDE Sleep Mode The KAD5512P has a selectable clock divider that can be set to divide by four, two or one (no division). By default, the tri-level CLKDIV pin selects the divisor (refer to “VCM Output” on page 20). This functionality can be overridden and controlled through the SPI, as shown in Table 11 ...
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... Table 15) are set on the output bus on alternating clock phases. The test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. 27 KAD5512P ADDRESS 0XC0: TEST_IO Bits 7:6 User Test Mode 0x93[2:0] OUTPUT FORMAT ...
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... Output Mode [2:0] 000 = Pin Control 001 = LVDS 2mA 010 = LVDS 3mA 100 = LVCMOS other codes = reserved 74 output_mode_B 75 config_status 76-BF reserved 28 KAD5512P TABLE 17. SPI MEMORY MAP Bit 6 Bit 5 Bit 4 Bit 3 LSB First Soft Reset Reserved Burst end address [7:0] Reserved Chip ID # ...
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... C6-FF Reserved NOTE: 15. At power-up, the DDR Enable bit logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal pull-up. 29 KAD5512P TABLE 17. SPI MEMORY MAP (Continued) Bit 6 Bit 5 Bit 4 Bit 3 Output Test Mode [3:0] ...
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... AVDD Ω 75kO 280O Ω INPUT Ω 75kO FIGURE 45. TRI-LEVEL DIGITAL INPUTS OVDD 2mA OR 3mA DATA DATA OVDD DATA DATA 2mA OR 3mA FIGURE 47. LVDS OUTPUTS 30 KAD5512P CLKP TO CHARGE PIPELINE Φ CHARGE PIPELINE CLKN Φ AVDD (20k PULL-UP ON RESETN TO SENSE LOGIC INPUT Ω ...
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... Bypass and Filtering Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close 31 KAD5512P (Continued) + – FIGURE 49. VCM_OUT OUTPUT to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy ...
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... The vias below the KAD5512P may be spaced further apart as shown on the evaluation board since low-power device. The via diameter should be small but not too small to allow solder wicking during reflow ...
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... Change to SPI interface section in spec table, timing in cycles now, added write, read specific timing specs. 18) Updated SPI timing diagrams, Figures 37, 38 19) Updated wakeup time description in “Nap/Sleep” on page 21. 20) Removed calibration note in spec table 21) Updated fig 46 label) 22) Updated cal paragraph in user initiated reset section per DC. 33 KAD5512P CHANGE FN6807.4 October 1, 2010 ...
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... Reset” on page 19. Added PAD connection information to “Pin Description” tables and pin configurations. Added “Recommended Operating Conditions” on page 9. Added typical “ICM” on page 9 for KAD5512P-21 along with descriptive text in the “Analog Input” section on page 20. Added “VCM Output” on page 20. ...
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... Package Outline Drawing L48.7x7E 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 2/09 7.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 6.80 Sq 5.60 Sq TYPICAL RECOMMENDED LAND PATTERN 35 KAD5512P Exp. DAP 7.00 5.60 Sq. 25 0.90 Max 44X 0.50 C 48X 0.25 48X 0.60 NOTES: 1 ...
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... Package Outline Drawing L72.10x10D 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08 10.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 9.80 Sq 6.00 Sq TYPICAL RECOMMENDED LAND PATTERN 36 KAD5512P 10. 72X 0.40 BOTTOM VIEW 0.90 Max 68X 0.50 72X 0. REF 72X 0.60 NOTES: 1. Dimensions are in millimeters. ...