ADC083000CIYB/NOPB National Semiconductor, ADC083000CIYB/NOPB Datasheet - Page 28

• Manufacturer Part Number: ADC083000CIYB/NOPB
• Description: IC ADC 8BIT 3GSPS LP 128-LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC083000CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 3G
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 2.3W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC083000CIYB; *ADC083000CIYB/NOPB; ADC083000CIYB

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1.4 REGISTER DESCRIPTION
Eight write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Normal Control
Mode. Each register description below also shows the Power-
On Reset (POR) state of each control bit.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Addr: 1h (0001b)
D15
D7
1
1
DRE RTD DCS DCP
D14
D6
1
Must be set to 1b
DRE: Differential Reset Enable. When this bit
is set to 0b , it enables the single-ended
DCLK_RST input. When this bit is set to 1b , it
enables the differential DCLK_RST input.
POR State: 0b
RTD: Resistor Trim Disable. When this bit is
set to 1b, the input termination resistor is not
trimmed during the calibration cycle and the
DCLK output remains enabled. Note that the
ADC is calibrated regardless of this setting.
POR State: 0b
DCS: Duty Cycle Stabilizer. When this bit is set
to 1b , a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disabled.
POR State: 1b
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set to
0b, the DCLK edges are time-aligned with the
data bus edges ("0° Phase"). When this bit is
set to 1b, the DCLK edges are placed in the
middle of the data bit-cells ("90° Phase"),
using the one-half speed DCLK shown in
Figure 4 as the phase reference.
POR State: 0b
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Dual Data
Rate) mode whereby a data word is output
with each rising and falling edge of DCLK.
When the device is in DDR mode, address 1h,
bit-8 must be set to 0b. When this bit is set to
a 1b, data bus clocking follows the SDR (single
data rate) mode whereby each data word is
output with either the rising or falling edge of
DCLK , as determined by the OutEdge bit.
POR State: 0b
D13
Configuration Register
D5
1
D12
D4
1
D11
D3
1
nDE
D10
D2
1
W only (0x92FF)
OV
D9
D1
1
OE
D8
D0
1
28
Bit 9
Bit 8
Bits 7:0
Bits 15:8
Bit 7
Bit 6:0
Addr: 2h (0010b)
(MSB)
Sign
D15
D7
D14
D6
1
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 680
mV
reduced output amplitude of 520 mV
used.
POR State: 1b
OE: Output Edge. This bit has two functions.
When the device is in SDR mode, this bit
selects the DCLK edge with which the data
words transition and has the same effect as
the OutEdge pin in the normal control mode.
When this bit is set to 1b, the data outputs
change with the rising edge of DCLK+. When
this bit is set to 0b, the data output changes
with the falling edge of DCLK+. When the
device is in DDR mode, this bit must be set to
0b.
POR State: 0b
Must be set to 1b
Offset Value. The input offset of the ADC is
adjusted linearly and monotonically by the
value in this field. 00h provides a nominal zero
offset, while FFh provides a nominal 45 mV of
offset. Thus, each code step provides 0.176
mV of offset.
POR State: 0000 0000 b (no adjustment)
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Must be set to 1b
P-P
D13
D5
1
is used. When this bit is set to 0b, the
Offset Adjust
Offset Value
D12
D4
1
D11
D3
1
D10
D2
1
W only (0x007F)
D9
D1
1
(LSB)
P-P
D8
D0
1
is