MAX1401EAI+ Maxim Integrated Products, MAX1401EAI+ Datasheet - Page 13

• Manufacturer Part Number: MAX1401EAI+
• Description: IC ADC 18BIT LP 28-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1401EAI+

• Number Of Bits: 18
• Sampling Rate (per Second): 480
• Data Interface: QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 750µW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Number Of Adc Inputs: 5
• Architecture: Delta-Sigma
• Conversion Rate: 4.8 KSPs
• Resolution: 18 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: External
• Supply Voltage (max): 3 V
• Maximum Power Dissipation: 21.45 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Signal Type: Pseudo-Differential, Differential
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX1401 is a low-power, multichannel, serial-
output, sigma-delta ADC designed for applications with
a wide dynamic range, such as weigh scales and pres-
sure transducers. The functional diagram in Figure 2
contains a switching network, a modulator, a PGA, two
buffers, an oscillator, an on-chip digital filter, and a
bidirectional serial communications port.
Three fully differential input channels feed into the
switching network. Each channel may be independent-
ly programmed with a gain between +1V/V and
+128V/V. These three differential channels may also be
configured to operate as five pseudo-differential input
channels. Two additional, fully differential system-cali-
bration channels allow system gain and offset error to
be measured. These system-calibration channels can
be used as additional differential signal channels when
dedicated gain and offset error correction channels are
not required.
Two chopper-stabilized buffers are available to isolate
the selected inputs from the capacitive loading of the
PGA and modulator. Three independent DACs provide
Figure 2. Functional Diagram
_______________Detailed Description
MUXOUT+
CALGAIN+
CALGAIN-
MUXOUT-
CALOFF+
CALOFF-
ADCIN+
ADCIN-
REFIN+
REFIN-
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
SWITCHING
NETWORK
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
AGND
V+
Circuit Description
Oversampling (Sigma-Delta) ADC
BUFFER
BUFFER
MAX1401
compensation for the DC component of the input signal
on each of the differential input channels.
The sigma-delta modulator converts the input signal into
a digital pulse train whose average duty cycle represents
the digitized signal information. The pulse train is then
processed by a digital decimation filter, resulting in a
conversion accuracy exceeding 16 bits. The digital filter’s
decimation factor is user-selectable, which allows the
conversion result’s resolution to be reduced to achieve a
higher output data rate. When used with 2.4576MHz or
1.024MHz master clocks, the decimation filter can be
programmed to produce zeros in its frequency response
at the line frequency and associated harmonics. This
ensures excellent line rejection without the need for fur-
ther post-filtering. In addition, the modulator sampling
frequency can be optimized for either lowest power dis-
sipation or highest output data rate.
The MAX1401 can be configured to sequentially scan
all signal inputs and to transmit the results through the
serial interface with minimum communications over-
head. The output word contains a channel identification
tag to indicate the source of each conversion result.
PGA
DAC
MODULATOR
DIVIDER
AND CONTROL
INTERFACE
DIGITAL
FILTER
CLOCK
GEN
CLKIN
CLKOUT
V
DGND
V+
AGND
SCLK
DIN
DOUT
INT
CS
RESET
DD
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