LTC2439-1IGN Linear Technology, LTC2439-1IGN Datasheet - Page 21

• Manufacturer Part Number: LTC2439-1IGN
• Description: IC ADC 16BIT 16CH MCRPWR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC2439-1IGN

• Number Of Bits: 16
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.150", 3.95mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Figure 12), a first order passive network with a time
constant τ = (R
sample the input signal with better than 1LSB accuracy if
the sampling period is at least 11 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (F
LTC2439-1’s front-end switched-capacitor network is
clocked at 69900Hz corresponding to a 14.3µs sampling
period. Thus, for settling errors of less than 1LSB, the
driving source impedance should be chosen such that
τ ≤ 14.3µs/11 = 1.3µs. When an external oscillator of
SWITCHING FREQUENCY
f
f
SW
SW
V
V
I
V
V
I
REF
REF
I
I
REF
REF
IN
IN
IN
IN
= 69900Hz INTERNAL OSCILLATOR (F
= 0.5 • f
+
+
–
–
+
+
–
–
V
V
EOSC
CC
CC
S
+ R
V
V
EXTERNAL OSCILLATOR
I
I
I
I
LEAK
LEAK
LEAK
LEAK
CC
CC
U
SW
I
I
I
I
LEAK
LEAK
LEAK
LEAK
) • C
U
R
R
R
R
SW
SW
SW
SW
EQ
20k
20k
20k
20k
(TYP)
(TYP)
(TYP)
(TYP)
. The converter is able to
O
W
= LOW)
Figure 12. LTC2439-1 Equivalent Analog Input Circuit
24391 F11
O
= LOW), the
C
18pF
(TYP)
U
EQ
frequency f
and, for a settling error of less than 1LSB, τ ≤ 0.18/f
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 12 shows the
mathematical expressions for the average bias currents
flowing through the IN
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
I IN
I IN
I REF
I REF
where
V
V
V
V
R
R
( )
( )
( )
( )
IN
INCM
REF
REFCM
EQ
EQ
+
−
=
=
=
=
+
−
IN
AVG
AVG
: :
=
3 97
(
REF
0 555 10
AVG
AVG
=
+
.
⎛
⎜
⎝
.
⎛
⎜
⎝
−
IN
=
=
M
REF
+
IN
=
V
=
+
−
Ω
IN
−
•
−
V
1 5
−
2
EOSC
−
IN
REF
.
+
+
1 5
IN
INTERNAL OSCILLATOR
.
+
2
12
V
+
•
0 5
−
INCM
0 5
V
REF
•
−
.
V
⎞
⎟
⎠
)
REF
INCM
.
/
V
is used, the sampling period is 2/f
f
•
EOSC
REF
•
R
0 5
−
−
R
−
0 5
EQ
.
⎞
⎟
⎠
EQ
.
V
−
−
V
•
EXTERNAL OSCILLATOR
REFCM
INCM
V
V
•
R
REFCM
INCM
+
R
EQ
EQ
and IN
+
+
V
REFCM
V
REFCM
–
50
−
pins as a result of the
+
Hz
V
LTC2439-1
REF
V
/
REF
60
V
IN
•
2
V
Hz Notch F
R
IN
•
2
EQ
R
EQ
(
O
21
=
EOSC
24391fa
LOW
EOSC
)
.