LTC2402CMS Linear Technology, LTC2402CMS Datasheet - Page 18

• Manufacturer Part Number: LTC2402CMS
• Description: IC ADC 24BIT 2CH MICROPWR 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC2402CMS

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC2401/LTC2402
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
(if EOC = 0) or t
during the falling edge of EOC). The value of t
if the device is using its internal oscillator (F
or HIGH). If F
frequency f
HIGH before time t
state. The conversion result is held in the internal static
shift register.
(INTERNAL)
18
SDO
SCK
CS
CONVERSION
EOSC
Hi-Z
O
EOCtest
, then t
is driven by an external oscillator of
EOCtest
U
after EOC goes LOW (if CS is LOW
TEST EOC
EOCtest
EOCtest
, the device remains in the sleep
U
SLEEP
Hi-Z
is 3.6/f
<t
after the falling edge of CS
EOCtest
BIT 31
EOC
W
Figure 8. Internal Serial Clock, Single Cycle Operation
EOSC
CH0/CH1
BIT 30
ANALOG INPUT RANGE
(V
. If CS is pulled
ZS
REF
REFERENCE VOLTAGE
0V TO FS
EOCtest
ZS
0
SET
FS
= FS
SET
= logic LOW
SET
– 0.12V
U
SET
+ 0.1V TO V
SET
+ 0.12V
BIT 29
SIG
– ZS
– 100mV
REF
is 23 s
SET
1 F
2.7V TO 5.5V
REF
TO
)
CC
BIT 28
EXR
1
2
3
4
5
V
FS
CH1
ZS
CH0
CC
SET
SET
LTC2402
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
BIT 27
MSB
DATA OUTPUT
SDO
GND
SCK
CS
F
O
10
9
8
7
6
BIT 26
V
CC
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
LSB
BIT 4
24
EOCtest
V
BIT 0
CC
10k
, the first rising
CONVERSION
Hi-Z
TEST EOC
2400 F08
Hi-Z