LTC2208CUP#TR Linear Technology, LTC2208CUP#TR Datasheet - Page 14

• Manufacturer Part Number: LTC2208CUP#TR
• Description: IC ADC 16BIT 130MSPS 64-QFN
• Manufacturer: Linear Technology

Specifications of LTC2208CUP#TR

• Number Of Bits: 16
• Sampling Rate (per Second): 130M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN FUNCTIONS
LTC2208
For CMOS Mode. Full Rate or Demultiplexed
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to V
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.
V
mon mode. Must be bypassed to ground with a minimum
of 2.2μF . Ceramic chip capacitors are recommended.
V
Bypass to GND with 1μF ceramic chip capacitors.
A
A
ENC
sampled analog input is held on the rising edge of ENC
Internally biased to 1.6V through a 6.2k resistor. Output
data can be latched on the rising edge of ENC
ENC
sampled analog input is held on the falling edge of ENC
Internally biased to 1.6V through a 6.2k resistor. Bypass to
ground with a 0.1μF capacitor for a single-ended Encode
signal.
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of this data sheet for details
on dither operation.
DB0-DB15 (Pins 21-30 and 33-38): Digital Outputs, B Bus.
DB15 is the MSB. Active in demultiplexed mode. The B
bus is in high impedance state in full rate CMOS.
OGND (Pins 31 and 50): Output Driver Ground.
OV
Drivers. Bypass to ground with 1μF capacitor.
OFB (Pin 39): Over/Under Flow Digital Output for the B Bus.
OFB is high when an over or under fl ow has occurred on the
B bus. At high impedance state in full rate CMOS mode.
14
CM
DD
IN
IN
DD
+
–
+
–
(Pin 3): 1.25V Output. Optimum voltage for input com-
(Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
(Pin 8): Positive Differential Analog Input.
(Pin 9): Negative Differential Analog Input.
(Pin 12): Positive Differential Encode Input. The
(Pin 13): Negative Differential Encode Input. The
(Pins 32 and 49): Positive Supply for the Output
DD
to select the internal
+
.
+
–
.
.
CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle
at the sample rate in full rate CMOS mode or at 1/2 the
sample rate in demultiplexed mode. Latch the data on the
falling edge of CLKOUTB.
CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA
will toggle at the sample rate in full rate CMOS mode or
at 1/2 the sample rate in demultiplexed mode. Latch the
data on the rising edge of CLKOUTA.
DA0-DA15 (Pins 42-48 and 51-59): Digital Outputs, A Bus.
DA15 is the MSB. Output bus for full rate CMOS mode
and demultiplexed mode.
OFA (Pin 60): Over/Under Flow Digital Output for the A
Bus. OFA is high when an over or under fl ow has occurred
on the A bus.
LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3V
LVDS to 2/3V
ing LVDS to V
MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3V
binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3V
output format and enables the clock duty cycle stabilizer.
Connecting MODE to V
format and disables the clock duty cycle stabilizer.
RAND (Pin 63): Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D15 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
PGA (Pin 64): Programmable Gain Amplifi er Control Pin. Low
selects a front-end gain of 1, input range of 2.25V
selects a front-end gain of 1.5, input range of 1.5V
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package must be soldered to
ground.
DD
selects demultiplexed CMOS mode. Connecting
DD
DD
selects Low Power LVDS mode. Connect-
selects Standard LVDS mode.
DD
selects 2’s complement output
DD
selects 2’s complement
DD
selects offset
P-P
P-P
. High
.
2208fc