AD7711AR Analog Devices Inc, AD7711AR Datasheet - Page 5

• Manufacturer Part Number: AD7711AR
• Description: IC ADC 24BIT RTD I SOURCE 24SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7711AR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 80°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 19.5KSPS
• Input Polarity: Unipolar/Bipolar
• Input Type: Voltage
• Rated Input Volt: 5/±5V
• Differential Input: Yes
• Power Supply Requirement: Single/Dual
• Single Supply Voltage (typ): 5/10V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 10.5V
• Dual Supply Voltage (typ): ±5/-5/10V
• Dual Supply Voltage (min): ±4.75V
• Dual Supply Voltage (max): -5.25/10.5V
• Power Dissipation: 52.5mW
• Integral Nonlinearity Error: ±0.003%FSR
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Not Compliant

TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
Self-Clocking Mode
NOTES
1
2
3
4
5
6
7
REV.G
CLK IN
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
See Figures 10 to 13.
The AD7711 is specified with a 10 MHz clock for AV
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711 is not in STANDBY mode. If no clock is present in this case, the device
The AD7711 is production tested with f
Specified using 10% and 90% points on waveform of interest.
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
CLK IN LO
CLK IN HI
r
f
1
than 10.5 V.
can draw higher current than specified and possibly become uncalibrated.
6
6
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2
3
4
5
6
7
8
9
10
14
15
16
17
18
19
7
7
4, 5
Limit at T
(A, S Versions)
400
10
0.4 × t
0.4 × t
50
50
1000
0
0
2 × t
0
4 × t
4 × t
t
t
t
3 × t
50
0
4 × t
4 × t
0
10
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
/2
/2 + 30
/2
/2
+ 20
+ 20
+ 20
at 10 MHz (8 MHz for AV
MIN
1, 2
, T
DD
MAX
(DV
0 V; f
voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AV
DD
CLK IN
= +5 V
= 10 MHz; Input Logic 0 = 0 V, Logic 1 = DV
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns nom
ns nom
ns min
ns min
ns max
ns min
ns min
ns min
DD
5%; AV
> 5.25 V). It is guaranteed by characterization to operate at 400 kHz.
–5–
DD
= +5 V or +10 V
Conditions/Comments
Master Clock Frequency: Crystal Oscillator or Externally
Supplied for Specified Performance
Master Clock Input Low Time; t
Master Clock Input High Time
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
SYNC Pulse Width
DRDY to RFS Setup Time
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
RFS Low to SCLK Falling Edge
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
A0 to TFS Setup Time
A0 to TFS Hold Time
TFS to SCLK Falling Edge Delay Time
TFS to SCLK Falling Edge Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
3
5%; V
SS
DD
= 0 V or –5 V
, unless otherwise noted.)
DD
voltages greater than 5.25 V and less
CLK IN
10%; AGND = DGND =
= 1/f
AD7711
CLK IN
2