AD9260ASZ Analog Devices Inc, AD9260ASZ Datasheet - Page 10
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AD9260ASZ
Manufacturer Part Number
AD9260ASZ
Description
IC ADC CMOS 16BIT OVRSAMP 44MQFP
Manufacturer
Analog Devices Inc
Datasheet
1.AD9260ASZRL.pdf
(44 pages)
Specifications of AD9260ASZ
Data Interface
Parallel
Number Of Bits
16
Sampling Rate (per Second)
20M
Number Of Converters
1
Power Dissipation (max)
585mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-MQFP, 44-PQFP
Resolution (bits)
16bit
Sampling Rate
2.5MSPS
Input Channel Type
Differential, Single Ended
Supply Voltage Range - Analog
4.75V To 5.25V
Number Of Elements
1
Resolution
16Bit
Architecture
Pipelined
Sample Rate
2.5MSPS
Input Polarity
Unipolar
Input Type
Voltage
Rated Input Volt
±0.8/±2V
Differential Input
Yes
Power Supply Requirement
Analog and Digital
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
5.25V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Differential Linearity Error
±0.5LSB(Typ)
Integral Nonlinearity Error
±0.75LSB(Typ)
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
MQFP
Input Signal Type
Differential
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9260ASZ
Manufacturer:
ADI
Quantity:
100
Company:
Part Number:
AD9260ASZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9260ASZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9260ASZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD9260
SWITCHING SPECIFICATIONS
AVDD = +5 V, DVDD = +5 V, C
Table 9.
Parameters
Clock Period
Data Available (DAV) Period
Data Invalid
Data Set-Up Time
Clock Pulse-Width High
Clock Pulse-Width Low
Data Hold Time
RESET to DAV Delay
CLOCK to DAV Delay
Three-State Output Disable Time
Three-State Output Enable Time
INPUT CLOCK
L
RESET
= 20 pF, T
DAV
MIN
to T
t
RES-DAV
MAX
unless otherwise noted.
Figure 9. RESET Timing Diagram
Rev. C | Page 10 of 44
t
CLK-DAV
Symbol
t
t
t
t
t
t
t
t
t
t
t
C
DAV
DI
DS
CH
CL
H
RES–DAV
CLK–DAV
OD
OE
AD9260
50
t
40% t
t
22.5
22.5
3.5
10
15
8
45
C
DAV
×Mode
–t
DAV
H
–t
DI
Unit
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ