ADC1175CIMTCX/NOPB National Semiconductor, ADC1175CIMTCX/NOPB Datasheet - Page 17

• Manufacturer Part Number: ADC1175CIMTCX/NOPB
• Description: ADC 8BIT 20MHZ 60MW 24-TSSOP
• Manufacturer: National Semiconductor

Specifications of ADC1175CIMTCX/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 20M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 60mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -20°C ~ 75°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC1175CIMTCX

each conversion, the more instantaneous digital current is re-
quired from DV
spikes can couple into the analog section, degrading dynamic
performance. Buffering the digital data outputs (with an
74AC541, for example) may be necessary if the data bus to
be driven is heavily loaded. Dynamic performance can also
be improved by adding 47Ω to 100Ω series resistors at each
digital output, reducing the energy coupled back into the con-
verter output pins.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.0, the capacitance seen at the input
alternates between 4 pF and 11 pF with the clock. This dy-
namic capacitance is more difficult to drive than is a fixed
capacitance, and should be considered when choosing a
driving device. The LMH6702, LMH6609, LM6152, LM6154,
LM6181 and LM6182 have been found to be excellent de-
vices for driving the ADC1175 analog input.
Driving the V
not source or sink the current required by the ladder. As
mentioned in section 2.0, care should be taken to see that any
driving devices can source sufficient current into the V
and sink sufficient current from the V
not driven with devices than can handle the required current,
these reference pins will not be stable, resulting in a reduction
of dynamic performance.
Using a clock source with excessive jitter, using an ex-
cessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR performance. Simple gates with RC timing
is generally inadequate as a clock source.
Input test signal contains harmonic distortion that inter-
feres with the measurement of dynamic signal to noise
ratio. Harmonic and other interfering signals can be removed
by inserting a filter at the signal input. Suitable filters are
shown in Figure 7 and Figure 8. The circuit of Figure 7 has
cutoff of about 5.5 MHz and is suitable for input frequencies
of 1 MHz to 5 MHz. The circuit of Figure 8 has a cutoff of about
11 MHz and is suitable for input frequencies of 5 MHz to 10
MHz. These filters should be driven by a generator of 75 Ohm
source impedance and terminated with a 75 ohm resistor.
RT
DD
pin or the V
and DGND. These large charging current
RB
pin with devices that can
RB
pin. If these pins are
RT
pin
17
FIGURE 8. 11 MHz Low Pass filter to eliminate harmonics
Not considering the effect on a driven CMOS digital cir-
cuit(s) when the ADC1175 is in the power down mode.
Because the ADC1175 output goes into a high impedance
state when in the power down mode, any CMOS device con-
nected to these outputs will have their inputs floating when
the ADC is in power down. Should the inputs of the circuit
being driven by the ADC digital outputs float to a level near
2.5V, a CMOS device could exhibit relative large supply cur-
rents as the input stage toggles rapidly. The solution is to use
pull-down resistors at the ADC outputs. The value of these
resistors is not critical, as long as they do not cause excessive
currents in the outputs of the ADC1175. Low pull-down resis-
tor values could result in degraded SNR and SINAD perfor-
mance of the ADC1175. Values between 5 kΩ and 100 kΩ
should work well.
at the signal input. Use at input frequencies of 5 MHz to
FIGURE 7. 5.5 MHz Low Pass Filter to Eliminate
Harmonics at the Signal Input.
10 MHz
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