AD7660AST Analog Devices Inc, AD7660AST Datasheet - Page 14

• Manufacturer Part Number: AD7660AST
• Description: IC ADC 16BIT UNIPOLAR 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7660AST

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 25mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: EVAL-AD7660CBZ - BOARD EVALUATION FOR AD7660

AD7660
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7660 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The CNVST signal operates independently of
CS and RD signals.
For a true sampling application, the recommended operation of
the CNVST signal is the following:
CNVST must be held HIGH from the previous falling edge
of BUSY, and during a minimum delay corresponding to the
acquisition time t
conversion is initiated and the BUSY signal goes HIGH until
the completion of the conversion. Although CNVST is a digital
signal, it should be designed with special care with fast, clean
edges and levels, with minimum overshoot and undershoot or
ringing. For applications where the SNR is critical, the CNVST
signal should have a very low jitter. This may be achieved by
using a dedicated oscillator for CNVST generation or, at least,
to clock it with a high frequency low jitter clock, as shown in
Figure 5.
For other applications, conversions can be automatically initiated.
If CNVST is held LOW when BUSY is LOW, the AD7660
controls the acquisition phase and then automatically initiates a
new conversion. By keeping CNVST LOW, the AD7660 keeps
the conversion process running by itself. It should be noted that
the analog input has to be settled when BUSY goes LOW. Also,
at power-up, CNVST should be brought LOW once to initiate
the conversion process. In this mode, the AD7660 could some-
times run slightly faster than the guaranteed limit of 100 kSPS.
CNVST
MODE
BUSY
DATABUS
CNVST
RESET
BUSY
ACQUIRE
t
t
3
5
Figure 11. Basic Conversion Timing
8
Figure 12. RESET Timing
t
; then, when CNVST is brought LOW, a
CONVERT
1
t
7
t
4
t
9
t
2
t
6
ACQUIRE
t
8
t
8
CONVERT
–14–
DATA BUS
DIGITAL INTERFACE
The AD7660 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7660 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7660
to the host system interface digital supply. Finally, by using the
OB/2C input pin, both twos complement or straight binary
coding can be used.
The two signals CS and RD control the interface. CS and RD
have a similar effect because they are together internally. When
at least one of these signals is HIGH, the interface outputs are
in high impedance. Usually, CS allows the selection of each
AD7660 in multicircuit applications and is held LOW in a
single AD7660 design. RD is generally used to enable the con-
version result on the data bus.
PARALLEL INTERFACE
The AD7660 is configured to use the parallel interface when the
SER/PAR is held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or during
the following conversion as shown, respectively, in Figures 14 and
15. When the data is read during the conversion, however, it is
recommended that it is read-only during the first half of the
conversion phase. This avoids any potential feedthrough between
voltage transients on the digital interface and the most critical
analog conversion circuitry.
DATA BUS
CNVST
CS = RD = 0
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
BUSY
BUSY
Figure 14. Slave Parallel Data Timing for Reading
(Read after Convert)
CS
RD
t
3
t
12
PREVIOUS CONVERSION DATA
CONVERSION
t
CURRENT
1
t
13
t
10
t
4
t
11
NEW DATA
REV. D